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Move all the copies of the romstage.inc rule to 

src/arch/i386/Makefile.inc

For that to work, I had to:
- Add a CONFIG_ROMCC variable
- Set that variable on all ROMCC boards
- conditionally choose romcc or gcc rule based on that variable
- remove those two rules from all the boards' Makefiles
- switch a couple of boards to HAVE_OPTION_TABLE, as they actually have.

Also remove the duplication of rules with the sole difference of if
they depend on option_table.h or not.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2010-02-09 12:21:10 +00:00
parent e4119ccff8
commit 2063197a4f
101 changed files with 79 additions and 389 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/arch/i386/Kconfig
View File

@ -49,6 +49,10 @@ config BIG_BOOTBLOCK
default n if TINY_BOOTBLOCK
default y
config ROMCC
bool
default n
config BOOTBLOCK_NORTHBRIDGE_INIT
string

21
src/arch/i386/Makefile.inc
View File

@ -66,6 +66,27 @@ $(obj)/coreboot.a: $(objs)
ifeq ($(crt0s),)
$(error crt0s are empty. If your board still uses crt0-y and ldscript-y: It shouldn't, we moved away from that in r5065)
endif
OPTION_TABLE_H:=
ifeq ($(CONFIG_HAVE_OPTION_TABLE),y)
OPTION_TABLE_H:=$(obj)/option_table.h
endif
ifeq ($(CONFIG_ROMCC),y)
ROMCCFLAGS ?= -mcpu=p2 -O2
$(obj)/mainboard/$(MAINBOARDDIR)/failover.inc: $(obj)/romcc $(src)/arch/i386/lib/failover.c
$(obj)/romcc $(ROMCCFLAGS) --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/romcc $(OPTION_TABLE_H) $(obj)/build.h
$(obj)/romcc $(ROMCCFLAGS) $(INCLUDES) $< -o $@
else
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $< -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif
endif
ifeq ($(CONFIG_TINY_BOOTBLOCK),y)

9
src/mainboard/Makefile.k8_CAR.inc
View File

@ -46,12 +46,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

9
src/mainboard/Makefile.k8_ck804.inc
View File

@ -51,12 +51,3 @@ ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/southbridge/nvidia/ck804/romstrap.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

17
src/mainboard/Makefile.romccboard.inc
View File

@ -67,20 +67,3 @@ obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o
obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o
obj-$(CONFIG_HAVE_HARD_RESET) += reset.o
ifdef POST_EVALUATION
ROMCCFLAGS ?= -mcpu=p2 -O2
$(obj)/mainboard/$(MAINBOARDDIR)/failover.inc: $(obj)/romcc $(src)/arch/i386/lib/failover.c
$(obj)/romcc $(ROMCCFLAGS) --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@
ifeq ($(CONFIG_HAVE_OPTION_TABLE),y)
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h $(obj)/build.h
$(obj)/romcc $(ROMCCFLAGS) $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
else
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/build.h
$(obj)/romcc $(ROMCCFLAGS) $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
endif
endif

1
src/mainboard/a-trend/atc-6220/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_A_TREND_ATC_6220
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256

1
src/mainboard/a-trend/atc-6240/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_A_TREND_ATC_6240
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83627HF
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256

1
src/mainboard/abit/be6-ii_v2_0/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_ABIT_BE6_II_V2_0
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256

1
src/mainboard/advantech/pcm-5820/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_ADVANTECH_PCM_5820
select NORTHBRIDGE_AMD_GX1
select SOUTHBRIDGE_AMD_CS5530
select SUPERIO_WINBOND_W83977F
select ROMCC
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC

9
src/mainboard/amd/db800/Makefile.inc
View File

@ -19,12 +19,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/build.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

9
src/mainboard/amd/dbm690t/Makefile.inc
View File

@ -46,12 +46,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

9
src/mainboard/amd/norwich/Makefile.inc
View File

@ -20,12 +20,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/build.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

9
src/mainboard/amd/pistachio/Makefile.inc
View File

@ -46,12 +46,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

1
src/mainboard/amd/rumba/Kconfig
View File

@ -24,6 +24,7 @@ config BOARD_AMD_RUMBA
select CPU_AMD_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5536
select ROMCC
select UDELAY_TSC
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256

9
src/mainboard/amd/serengeti_cheetah/Makefile.inc
View File

@ -51,12 +51,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

10
src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc
View File

@ -49,13 +49,3 @@ ldscripts := $(src)/arch/i386/init/ldscript_fallback_cbfs.lb
ldscripts += $(src)/cpu/x86/32bit/entry32.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

9
src/mainboard/artecgroup/dbe61/Makefile.inc
View File

@ -20,12 +20,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

1
src/mainboard/asi/mb_5blgp/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_ASI_MB_5BLGP
select NORTHBRIDGE_AMD_GX1
select SOUTHBRIDGE_AMD_CS5530
select SUPERIO_NSC_PC87351
select ROMCC
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC

1
src/mainboard/asi/mb_5blmp/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_ASI_MB_5BLMP
select NORTHBRIDGE_AMD_GX1
select SOUTHBRIDGE_AMD_CS5530
select SUPERIO_NSC_PC87351
select ROMCC
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC

9
src/mainboard/asus/a8n_e/Makefile.inc
View File

@ -43,12 +43,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

9
src/mainboard/asus/a8v-e_se/Makefile.inc
View File

@ -25,12 +25,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

9
src/mainboard/asus/m2v-mx_se/Makefile.inc
View File

@ -37,12 +37,3 @@ crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
ldscripts := $(src)/arch/i386/init/ldscript_fallback_cbfs.lb
ldscripts += $(src)/cpu/x86/32bit/entry32.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

1
src/mainboard/asus/mew-am/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_ASUS_MEW_AM
select NORTHBRIDGE_INTEL_I82810
select SOUTHBRIDGE_INTEL_I82801XX
select SUPERIO_SMSC_SMSCSUPERIO
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512

1
src/mainboard/asus/mew-vm/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_ASUS_MEW_VM
select NORTHBRIDGE_INTEL_I82810
select SOUTHBRIDGE_INTEL_I82801XX
select SUPERIO_SMSC_LPC47B272
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512

1
src/mainboard/asus/p2b-d/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_ASUS_P2B_D
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
select ROMCC
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SMP

1
src/mainboard/asus/p2b-ds/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_ASUS_P2B_DS
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
select ROMCC
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SMP

1
src/mainboard/asus/p2b-f/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_ASUS_P2B_F
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256

1
src/mainboard/asus/p2b/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_ASUS_P2B
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256

1
src/mainboard/asus/p3b-f/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_ASUS_P3B_F
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256

1
src/mainboard/axus/tc320/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_AXUS_TC320
select NORTHBRIDGE_AMD_GX1
select SOUTHBRIDGE_AMD_CS5530
select SUPERIO_NSC_PC97317
select ROMCC
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC

1
src/mainboard/azza/pt-6ibd/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_AZZA_PT_6IBD
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256

1
src/mainboard/bcom/winnet100/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_BCOM_WINNET100
select NORTHBRIDGE_AMD_GX1
select SOUTHBRIDGE_AMD_CS5530
select SUPERIO_NSC_PC97317
select ROMCC
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC

9
src/mainboard/bcom/winnetp680/Makefile.inc
View File

@ -42,12 +42,3 @@ crt0s += $(src)/cpu/x86/fpu_enable.inc
crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
crt0s += $(src)/cpu/x86/mmx_disable.inc
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

1
src/mainboard/biostar/m6tba/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_BIOSTAR_M6TBA
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_SMSC_SMSCSUPERIO
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256

1
src/mainboard/compaq/deskpro_en_sff_p600/Kconfig
View File

@ -26,6 +26,7 @@ config BOARD_COMPAQ_DESKPRO_EN_SFF_P600
select SOUTHBRIDGE_INTEL_I82371EB
# should be SUPERIO_NSC_PC97307!
select SUPERIO_NSC_PC97317
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256

1
src/mainboard/dell/s1850/Kconfig
View File

@ -6,6 +6,7 @@ config BOARD_DELL_S1850
select SOUTHBRIDGE_INTEL_I82801ER
select SOUTHBRIDGE_INTEL_PXHD
select SUPERIO_NSC_PC8374
select ROMCC
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_1024

1
src/mainboard/digitallogic/adl855pc/Kconfig
View File

@ -5,6 +5,7 @@ config BOARD_DIGITALLOGIC_ADL855PC
select NORTHBRIDGE_INTEL_I855PM
select SOUTHBRIDGE_INTEL_I82801DBM
select SUPERIO_WINBOND_W83627HF
select ROMCC
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_1024

1
src/mainboard/digitallogic/msm586seg/Kconfig
View File

@ -4,6 +4,7 @@ config BOARD_DIGITALLOGIC_MSM586SEG
select CPU_AMD_SC520
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_512
select ROMCC
config MAINBOARD_DIR
string

9
src/mainboard/digitallogic/msm800sev/Makefile.inc
View File

@ -20,12 +20,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/build.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

1
src/mainboard/eaglelion/5bcm/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_EAGLELION_5BCM
select NORTHBRIDGE_AMD_GX1
select SOUTHBRIDGE_AMD_CS5530
select SUPERIO_NSC_PC97317
select ROMCC
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC

1
src/mainboard/emulation/qemu-x86/Kconfig
View File

@ -3,6 +3,7 @@ config BOARD_EMULATION_QEMU_X86
select ARCH_X86
select SOUTHBRIDGE_INTEL_I82371EB
select CPU_EMULATION_QEMU_X86
select ROMCC
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
select WARNINGS_ARE_ERRORS

1
src/mainboard/gigabyte/ga-6bxc/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_GIGABYTE_GA_6BXC
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_ITE_IT8671F
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256

5
src/mainboard/gigabyte/ga_2761gxdk/Makefile.inc
View File

@ -51,9 +51,4 @@ ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

5
src/mainboard/gigabyte/m57sli/Makefile.inc
View File

@ -56,9 +56,4 @@ ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

1
src/mainboard/hp/e_vectra_p2706t/Kconfig
View File

@ -28,6 +28,7 @@ config BOARD_HP_E_VECTRA_P2706T
select NORTHBRIDGE_INTEL_I82810
select SOUTHBRIDGE_INTEL_I82801XX
select SUPERIO_NSC_PC87360
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512

1
src/mainboard/iei/juki-511p/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_IEI_JUKI_511P
select NORTHBRIDGE_AMD_GX1
select SOUTHBRIDGE_AMD_CS5530
select SUPERIO_WINBOND_W83977F
select ROMCC
select PIRQ_ROUTE
select HAVE_OPTION_TABLE
select BOARD_ROMSIZE_KB_256

1
src/mainboard/iei/nova4899r/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_IEI_NOVA_4899R
select NORTHBRIDGE_AMD_GX1
select SOUTHBRIDGE_AMD_CS5530
select SUPERIO_WINBOND_W83977TF
select ROMCC
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select HAVE_OPTION_TABLE

9
src/mainboard/iei/pcisa-lx-800-r10/Makefile.inc
View File

@ -20,12 +20,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/build.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

9
src/mainboard/intel/d945gclf/Makefile.inc
View File

@ -49,12 +49,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

9
src/mainboard/intel/eagleheights/Makefile.inc
View File

@ -24,12 +24,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

1
src/mainboard/intel/jarrell/Kconfig
View File

@ -6,6 +6,7 @@ config BOARD_INTEL_JARRELL
select SOUTHBRIDGE_INTEL_PXHD
select SOUTHBRIDGE_INTEL_I82801ER
select SUPERIO_NSC_PC87427
select ROMCC
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select UDELAY_TSC

1
src/mainboard/intel/mtarvon/Kconfig
View File

@ -5,6 +5,7 @@ config BOARD_INTEL_MTARVON
select NORTHBRIDGE_INTEL_I3100
select SOUTHBRIDGE_INTEL_I3100
select SUPERIO_INTEL_I3100
select ROMCC
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select UDELAY_TSC

1
src/mainboard/intel/truxton/Kconfig
View File

@ -6,6 +6,7 @@ config BOARD_INTEL_TRUXTON
select SOUTHBRIDGE_INTEL_I3100
select SUPERIO_INTEL_I3100
select SUPERIO_SMSC_SMSCSUPERIO
select ROMCC
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select UDELAY_TSC

1
src/mainboard/intel/xe7501devkit/Kconfig
View File

@ -6,6 +6,7 @@ config BOARD_INTEL_XE7501DEVKIT
select SOUTHBRIDGE_INTEL_I82870
select SOUTHBRIDGE_INTEL_I82801CA
select SUPERIO_SMSC_LPC47B272
select ROMCC
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select UDELAY_TSC

9
src/mainboard/iwill/dk8_htx/Makefile.inc
View File

@ -50,12 +50,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

9
src/mainboard/jetway/j7f24/Makefile.inc
View File

@ -38,12 +38,3 @@ crt0s += $(src)/cpu/x86/fpu_enable.inc
crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
crt0s += $(src)/cpu/x86/mmx_disable.inc
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

9
src/mainboard/kontron/986lcd-m/Makefile.inc
View File

@ -45,12 +45,3 @@ crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
ldscripts := $(src)/arch/i386/init/ldscript_fallback_cbfs.lb
ldscripts += $(src)/cpu/x86/32bit/entry32.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

9
src/mainboard/kontron/kt690/Makefile.inc
View File

@ -46,12 +46,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

1
src/mainboard/lippert/frontrunner/Kconfig
View File

@ -4,6 +4,7 @@ config BOARD_LIPPERT_FRONTRUNNER
select CPU_AMD_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5535
select ROMCC
select UDELAY_TSC
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256

9
src/mainboard/lippert/roadrunner-lx/Makefile.inc
View File

@ -20,12 +20,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/build.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

9
src/mainboard/lippert/spacerunner-lx/Makefile.inc
View File

@ -20,12 +20,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/build.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

1
src/mainboard/mitac/6513wu/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_MITAC_6513WU
select NORTHBRIDGE_INTEL_I82810
select SOUTHBRIDGE_INTEL_I82801XX
select SUPERIO_SMSC_SMSCSUPERIO
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512

1
src/mainboard/msi/ms6119/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_MSI_MS_6119
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256

1
src/mainboard/msi/ms6147/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_MSI_MS_6147
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256

1
src/mainboard/msi/ms6156/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_MSI_MS_6156
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256

1
src/mainboard/msi/ms6178/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_MSI_MS_6178
select NORTHBRIDGE_INTEL_I82810
select SOUTHBRIDGE_INTEL_I82801XX
select SUPERIO_WINBOND_W83627HF
select ROMCC
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_512

5
src/mainboard/msi/ms7260/Makefile.inc
View File

@ -51,9 +51,4 @@ ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

5
src/mainboard/msi/ms9282/Makefile.inc
View File

@ -53,9 +53,4 @@ ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

1
src/mainboard/nec/powermate2000/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_NEC_POWERMATE_2000
select NORTHBRIDGE_INTEL_I82810
select SOUTHBRIDGE_INTEL_I82801XX
select SUPERIO_SMSC_SMSCSUPERIO
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512

5
src/mainboard/nvidia/l1_2pvv/Makefile.inc
View File

@ -53,9 +53,4 @@ ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

1
src/mainboard/olpc/btest/Kconfig
View File

@ -4,6 +4,7 @@ config BOARD_OLPC_BTEST
select CPU_AMD_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5536
select ROMCC
select UDELAY_TSC
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256

1
src/mainboard/olpc/rev_a/Kconfig
View File

@ -4,6 +4,7 @@ config BOARD_OLPC_REV_A
select CPU_AMD_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5536
select ROMCC
select UDELAY_TSC
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256

9
src/mainboard/pcengines/alix1c/Makefile.inc
View File

@ -20,12 +20,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

1
src/mainboard/rca/rm4100/Kconfig
View File

@ -5,6 +5,7 @@ config BOARD_RCA_RM4100
select NORTHBRIDGE_INTEL_I82830
select SOUTHBRIDGE_INTEL_I82801XX
select SUPERIO_SMSC_SMSCSUPERIO
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512

9
src/mainboard/roda/rk886ex/Makefile.inc
View File

@ -53,12 +53,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

1
src/mainboard/soyo/sy-6ba-plus-iii/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_SOYO_SY_6BA_PLUS_III
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_ITE_IT8671F
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256

9
src/mainboard/supermicro/h8dme/Makefile.inc
View File

@ -46,12 +46,3 @@ ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/southbridge/nvidia/mcp55/romstrap.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

9
src/mainboard/supermicro/h8dmr/Makefile.inc
View File

@ -45,12 +45,3 @@ ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/southbridge/nvidia/mcp55/romstrap.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

9
src/mainboard/supermicro/h8dmr_fam10/Makefile.inc
View File

@ -38,12 +38,3 @@ ldscripts := $(src)/arch/i386/init/ldscript_fallback_cbfs.lb
ldscripts += $(src)/cpu/x86/32bit/entry32.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

9
src/mainboard/supermicro/h8qme_fam10/Makefile.inc
View File

@ -38,12 +38,3 @@ ldscripts := $(src)/arch/i386/init/ldscript_fallback_cbfs.lb
ldscripts += $(src)/cpu/x86/32bit/entry32.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

1
src/mainboard/supermicro/x6dai_g/Kconfig
View File

@ -5,6 +5,7 @@ config BOARD_SUPERMICRO_X6DAI_G
select NORTHBRIDGE_INTEL_E7525
select SOUTHBRIDGE_INTEL_ESB6300
select SUPERIO_WINBOND_W83627HF
select ROMCC
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_1024

1
src/mainboard/supermicro/x6dhe_g/Kconfig
View File

@ -6,6 +6,7 @@ config BOARD_SUPERMICRO_X6DHE_G
select SOUTHBRIDGE_INTEL_ESB6300
select SOUTHBRIDGE_INTEL_PXHD
select SUPERIO_WINBOND_W83627HF
select ROMCC
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_1024

1
src/mainboard/supermicro/x6dhe_g2/Kconfig
View File

@ -6,6 +6,7 @@ config BOARD_SUPERMICRO_X6DHE_G2
select SOUTHBRIDGE_INTEL_I82801ER
select SOUTHBRIDGE_INTEL_PXHD
select SUPERIO_NSC_PC87427
select ROMCC
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_1024

1
src/mainboard/supermicro/x6dhr_ig/Kconfig
View File

@ -6,6 +6,7 @@ config BOARD_SUPERMICRO_X6DHR_IG
select SOUTHBRIDGE_INTEL_I82801ER
select SOUTHBRIDGE_INTEL_PXHD
select SUPERIO_WINBOND_W83627HF
select ROMCC
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_1024

1
src/mainboard/supermicro/x6dhr_ig2/Kconfig
View File

@ -6,6 +6,7 @@ config BOARD_SUPERMICRO_X6DHR_IG2
select SOUTHBRIDGE_INTEL_I82801ER
select SOUTHBRIDGE_INTEL_PXHD
select SUPERIO_WINBOND_W83627HF
select ROMCC
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_1024

9
src/mainboard/technexion/tim5690/Makefile.inc
View File

@ -52,12 +52,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

9
src/mainboard/technexion/tim8690/Makefile.inc
View File

@ -46,12 +46,3 @@ ldscripts += $(src)/cpu/x86/16bit/reset16.lds
ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

1
src/mainboard/technologic/ts5300/Kconfig
View File

@ -2,6 +2,7 @@ config BOARD_TECHNOLOGIC_TS5300
bool "TS-5300"
select ARCH_X86
select CPU_AMD_SC520
select ROMCC
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_128

1
src/mainboard/televideo/tc7020/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_TELEVIDEO_TC7020
select NORTHBRIDGE_AMD_GX1
select SOUTHBRIDGE_AMD_CS5530
select SUPERIO_NSC_PC97317
select ROMCC
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC

1
src/mainboard/thomson/ip1000/Kconfig
View File

@ -5,6 +5,7 @@ config BOARD_THOMSON_IP1000
select NORTHBRIDGE_INTEL_I82830
select SOUTHBRIDGE_INTEL_I82801XX
select SUPERIO_SMSC_SMSCSUPERIO
select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512

1
src/mainboard/tyan/s1846/Kconfig
View File

@ -25,6 +25,7 @@ config BOARD_TYAN_S1846
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_NSC_PC87309
select ROMCC
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256

9
src/mainboard/tyan/s2735/Makefile.inc
View File

@ -49,12 +49,3 @@ ldscripts += $(src)/arch/i386/lib/id.lds
ldscripts += $(src)/arch/i386/lib/failover.lds
ldscripts += $(src)/cpu/x86/car/cache_as_ram.lds
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

5
src/mainboard/tyan/s2912/Makefile.inc
View File

@ -53,9 +53,4 @@ ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

5
src/mainboard/tyan/s2912_fam10/Makefile.inc
View File

@ -46,9 +46,4 @@ ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

1
src/mainboard/via/epia-cn/Kconfig
View File

@ -5,6 +5,7 @@ config BOARD_VIA_EPIA_CN
select NORTHBRIDGE_VIA_CN700
select SOUTHBRIDGE_VIA_VT8237R
select SUPERIO_VIA_VT1211
select ROMCC
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_512

9
src/mainboard/via/epia-m/Makefile.inc
View File

@ -44,12 +44,3 @@ crt0s += $(src)/cpu/x86/fpu_enable.inc
crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
crt0s += $(src)/cpu/x86/mmx_disable.inc
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

12
src/mainboard/via/epia-m700/Makefile.inc
View File

@ -44,15 +44,3 @@ crt0s += $(src)/arch/i386/lib/id.inc
crt0s += $(src)/cpu/via/car/cache_as_ram.inc
crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.c
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

9
src/mainboard/via/epia-n/Makefile.inc
View File

@ -41,12 +41,3 @@ crt0s += $(src)/cpu/x86/fpu_enable.inc
crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
crt0s += $(src)/cpu/x86/mmx_disable.inc
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

9
src/mainboard/via/epia/Makefile.inc
View File

@ -37,12 +37,3 @@ crt0s += $(src)/cpu/x86/fpu_enable.inc
crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
crt0s += $(src)/cpu/x86/mmx_disable.inc
ifdef POST_EVALUATION
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

1
src/mainboard/via/pc2500e/Kconfig
View File

@ -5,6 +5,7 @@ config BOARD_VIA_PC2500E
select NORTHBRIDGE_VIA_CN700
select SOUTHBRIDGE_VIA_VT8237R
select SUPERIO_ITE_IT8716F
select ROMCC
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SMP

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