soc/amd: Change Morgana codename to Phoenix

Now that the next generation of APUs is officially announced, we can
unmask morgana.

The chip formerly known as Morgana is actually Phoenix.

Surprise!

This patch just changes the name across the entire codebase.

Note that the fw.cfg file will stay pointing to the
3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is
updated.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

MAINTAINERS

@@ -815,15 +815,15 @@ S:	Supported
 F:	src/soc/amd/mendocino/
 F:	src/vendorcode/amd/fsp/mendocino/
 
-AMD Morgana
+AMD Phoenix
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Fred Reitberger <reitbergerfred@gmail.com>
 M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
 L:	amd_coreboot_org_changes@googlegroups.com
 S:	Supported
-F:	src/soc/amd/morgana/
-F:	src/vendorcode/amd/fsp/morgana/
+F:	src/soc/amd/phoenix/
+F:	src/vendorcode/amd/fsp/phoenix/
 
 AMD Stoneyridge
 M:	Felix Held <felix-coreboot@felixheld.de>

src/mainboard/amd/birman/Kconfig

@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-if BOARD_AMD_BIRMAN_GLINDA || BOARD_AMD_BIRMAN_MORGANA
+if BOARD_AMD_BIRMAN_GLINDA || BOARD_AMD_BIRMAN_PHOENIX
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
@@ -24,11 +24,11 @@ config MAINBOARD_DIR
 
 config MAINBOARD_PART_NUMBER
 	default "Birman_Glinda" if BOARD_AMD_BIRMAN_GLINDA
-	default "Birman_Morgana"
+	default "Birman_Phoenix"
 
 config DEVICETREE
 	default "devicetree_glinda.cb" if BOARD_AMD_BIRMAN_GLINDA
-	default "devicetree_morgana.cb"
+	default "devicetree_phoenix.cb"
 
 config AMD_FWM_POSITION_INDEX
 	int
@@ -79,7 +79,7 @@ config RO_REGION_ONLY
 	string
 	depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A
 	# Add the EFS and EC to the RO region only
-	# This is a birman-specific override of soc/amd/(morgana | glinda)/Kconfig
+	# This is a birman-specific override of soc/amd/(phoenix | glinda)/Kconfig
 	default "apu/amdfw apu/ecfw"
 
 config CHROMEOS
@@ -109,4 +109,4 @@ config TPM_SPI_SPEED
 
 endif # !EM100
 
-endif # BOARD_AMD_BIRMAN_GLINDA || BOARD_AMD_BIRMAN_MORGANA
+endif # BOARD_AMD_BIRMAN_GLINDA || BOARD_AMD_BIRMAN_PHOENIX

src/mainboard/amd/birman/Kconfig.name

@@ -1,8 +1,8 @@
 comment "Birman"
 
-config BOARD_AMD_BIRMAN_MORGANA
-	bool "->  Birman for Morgana SoC"
-	select SOC_AMD_MORGANA
+config BOARD_AMD_BIRMAN_PHOENIX
+	bool "->  Birman for Phoenix SoC"
+	select SOC_AMD_PHOENIX
 
 config BOARD_AMD_BIRMAN_GLINDA
 	bool "->  Birman for Glinda SoC"

src/mainboard/amd/birman/devicetree_phoenix.cb

@@ -2,7 +2,7 @@
 
 # TODO: Update for birman
 
-chip soc/amd/morgana
+chip soc/amd/phoenix
 	register "common_config.espi_config" = "{
 		.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN,
 		.generic_io_range[0] = {

src/mainboard/amd/mayan/Kconfig

@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-if BOARD_AMD_MAYAN_MORGANA
+if BOARD_AMD_MAYAN_PHOENIX
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
@@ -23,10 +23,10 @@ config MAINBOARD_DIR
 	default "amd/mayan"
 
 config MAINBOARD_PART_NUMBER
-	default "Mayan_Morgana"
+	default "Mayan_Phoenix"
 
 config DEVICETREE
-	default "devicetree_morgana.cb"
+	default "devicetree_phoenix.cb"
 
 config AMD_FWM_POSITION_INDEX
 	int
@@ -77,7 +77,7 @@ config RO_REGION_ONLY
 	string
 	depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A
 	# Add the EFS and EC to the RO region only
-	# This is a mayan-specific override of soc/amd/morgana/Kconfig
+	# This is a mayan-specific override of soc/amd/phoenix/Kconfig
 	default "apu/amdfw ec/ecfw"
 
 config CHROMEOS
@@ -107,4 +107,4 @@ config TPM_SPI_SPEED
 
 endif # !EM100
 
-endif # BOARD_AMD_MAYAN_MORGANA
+endif # BOARD_AMD_MAYAN_PHOENIX

src/mainboard/amd/mayan/Kconfig.name

@@ -1,5 +1,5 @@
 comment "Mayan"
 
-config BOARD_AMD_MAYAN_MORGANA
-	bool "->  Mayan for Morgana SoC"
-	select SOC_AMD_MORGANA
+config BOARD_AMD_MAYAN_PHOENIX
+	bool "->  Mayan for Phoenix SoC"
+	select SOC_AMD_PHOENIX

src/mainboard/amd/mayan/devicetree_phoenix.cb

@@ -2,7 +2,7 @@
 
 # TODO: Update for mayan
 
-chip soc/amd/morgana
+chip soc/amd/phoenix
 	register "common_config.espi_config" = "{
 		.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN,
 		.generic_io_range[0] = {

src/mainboard/amd/mayan/gpio.c

@@ -139,7 +139,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 	/* CLK_REQ2_L */
 	PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE),
 	/* GPIO_117 - GPIO_129: Not available */
-	/* SATA_ACT_L - morgana does not have SATA, so force inactive */
+	/* SATA_ACT_L - phoenix does not have SATA, so force inactive */
 	PAD_GPO(GPIO_130, HIGH),
 	/* CLK_REQ3_L */
 	PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE),

src/soc/amd/morgana/include/soc/cpu.h

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_MORGANA_CPU_H
-#define AMD_MORGANA_CPU_H
-
-#define MORGANA_A0_CPUID	0x00a70f80
-
-#endif /* AMD_MORGANA_CPU_H */

src/soc/amd/morgana/include/soc/espi.h

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* TODO: Update for Morgana */
-
-#ifndef AMD_MORGANA_ESPI_H
-#define AMD_MORGANA_ESPI_H
-
-void espi_switch_to_spi1_pads(void);
-
-#endif /* AMD_MORGANA_ESPI_H */

src/soc/amd/phoenix/Kconfig

@@ -1,9 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
 # TODO: Evaluate what can be moved to a common directory
-# TODO: Update for Morgana
+# TODO: Update for Phoenix
 
-config SOC_AMD_MORGANA
+config SOC_AMD_PHOENIX
 	bool
 	select ACPI_SOC_NVS
 	select ARCH_X86
@@ -82,13 +82,13 @@ config SOC_AMD_MORGANA
 	select X86_AMD_FIXED_MTRRS
 	select X86_INIT_NEED_1_SIPI
 	help
-	  AMD Morgana support
+	  AMD Phoenix support
 
-if SOC_AMD_MORGANA
+if SOC_AMD_PHOENIX
 
 config CHIPSET_DEVICETREE
 	string
-	default "soc/amd/morgana/chipset.cb"
+	default "soc/amd/phoenix/chipset.cb"
 
 config EARLY_RESERVED_DRAM_BASE
 	hex
@@ -342,7 +342,7 @@ comment "AMD Firmware Directory Table set to location for 16MB ROM"
 
 config AMDFW_CONFIG_FILE
 	string "AMD PSP Firmware config file"
-	default "src/soc/amd/morgana/fw.cfg"
+	default "src/soc/amd/phoenix/fw.cfg"
 	help
 	  Specify the path/location of AMD PSP Firmware config file.
 
@@ -386,7 +386,7 @@ config HAVE_PSP_WHITELIST_FILE
 config PSP_WHITELIST_FILE
 	string "Debug whitelist file path"
 	depends on HAVE_PSP_WHITELIST_FILE
-	default "site-local/3rdparty/amd_blobs/morgana/PSP/wtl-mrg.sbin"
+	default "site-local/3rdparty/amd_blobs/phoenix/PSP/wtl-phx.sbin"
 
 config HAVE_SPL_FILE
 	bool "Have a mainboard specific SPL table file"
@@ -403,7 +403,7 @@ config HAVE_SPL_FILE
 config SPL_TABLE_FILE
 	string "SPL table file"
 	depends on HAVE_SPL_FILE
-	default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_MRG.sbin"
+	default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_PHX.sbin"
 
 config HAVE_SPL_RW_AB_FILE
 	bool "Have a separate mainboard-specific SPL file in RW A/B partitions"
@@ -418,7 +418,7 @@ config HAVE_SPL_RW_AB_FILE
 config SPL_RW_AB_TABLE_FILE
 	string "Separate SPL table file for RW A/B partitions"
 	depends on HAVE_SPL_RW_AB_FILE
-	default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_MRG.sbin"
+	default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_PHX.sbin"
 
 config PSP_SOFTFUSE_BITS
 	string "PSP Soft Fuse bits to enable"

src/soc/amd/phoenix/Makefile.inc

@@ -1,9 +1,9 @@
 # SPDX-License-Identifier: BSD-3-Clause
 
 # TODO: Move as much as possible to common
-# TODO: Update for Morgana
+# TODO: Update for Phoenix
 
-ifeq ($(CONFIG_SOC_AMD_MORGANA),y)
+ifeq ($(CONFIG_SOC_AMD_PHOENIX),y)
 
 subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
 
@@ -51,9 +51,9 @@ smm-y		+= smihandler.c
 smm-y		+= smu.c
 smm-$(CONFIG_DEBUG_SMI) += uart.c
 
-CPPFLAGS_common += -I$(src)/soc/amd/morgana/include
-CPPFLAGS_common += -I$(src)/soc/amd/morgana/acpi
-CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/morgana
+CPPFLAGS_common += -I$(src)/soc/amd/phoenix/include
+CPPFLAGS_common += -I$(src)/soc/amd/phoenix/acpi
+CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/phoenix
 CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common
 
 MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR)
@@ -69,7 +69,7 @@ MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR)
 $(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\
      $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size))
 
-MORGANA_FWM_POSITION=$(call int-add, \
+PHOENIX_FWM_POSITION=$(call int-add, \
 	$(call int-subtract, 0xffffffff \
 	$(call int-shift-left, \
 	0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1)
@@ -78,11 +78,11 @@ MORGANA_FWM_POSITION=$(call int-add, \
 # Building the cbfs image will fail if the offset isn't large enough
 AMD_FW_AB_POSITION := 0x40
 
-MORGANA_FW_A_POSITION=$(call int-add, \
+PHOENIX_FW_A_POSITION=$(call int-add, \
 	$(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \
 	$(AMD_FW_AB_POSITION))
 
-MORGANA_FW_B_POSITION=$(call int-add, \
+PHOENIX_FW_B_POSITION=$(call int-add, \
 	$(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \
 	$(AMD_FW_AB_POSITION))
 #
@@ -237,7 +237,7 @@ AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \
 		$(OPT_EFS_SPI_SPEED) \
 		$(OPT_EFS_SPI_MICRON_FLAG) \
 		--config $(CONFIG_AMDFW_CONFIG_FILE) \
-		--soc-name "Morgana" \
+		--soc-name "Phoenix" \
 		--flashsize $(CONFIG_ROM_SIZE) \
 		$(OPT_RECOVERY_AB_SINGLE_COPY)
 
@@ -259,7 +259,7 @@ $(obj)/amdfw.rom:	$(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
 		$(OPT_VERSTAGE_FILE) \
 		$(OPT_VERSTAGE_SIG_FILE) \
 		$(OPT_SPL_TABLE_FILE) \
-		--location $(shell printf "%#x" $(MORGANA_FWM_POSITION)) \
+		--location $(shell printf "%#x" $(PHOENIX_FWM_POSITION)) \
 		--output $@
 
 $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
@@ -278,7 +278,7 @@ $(obj)/amdfw_a.rom: $(obj)/amdfw.rom
 		$(OPT_SPL_RW_AB_TABLE_FILE) \
 		$(OPT_SIGNED_AMDFW_A_POSITION) \
 		$(OPT_SIGNED_AMDFW_A_FILE) \
-		--location $(shell printf "%#x" $(MORGANA_FW_A_POSITION)) \
+		--location $(shell printf "%#x" $(PHOENIX_FW_A_POSITION)) \
 		--anywhere \
 		--output $@
 
@@ -292,7 +292,7 @@ $(obj)/amdfw_b.rom: $(obj)/amdfw.rom
 		$(OPT_SPL_RW_AB_TABLE_FILE) \
 		$(OPT_SIGNED_AMDFW_B_POSITION) \
 		$(OPT_SIGNED_AMDFW_B_FILE) \
-		--location $(shell printf "%#x" $(MORGANA_FW_B_POSITION)) \
+		--location $(shell printf "%#x" $(PHOENIX_FW_B_POSITION)) \
 		--anywhere \
 		--output $@
 
@@ -320,4 +320,4 @@ build_complete:: $(obj)/amdfw_a.rom $(obj)/amdfw_b.rom
 endif # CONFIG_SEPARATE_SIGNED_PSPFW
 endif
 
-endif # ($(CONFIG_SOC_AMD_MORGANA),y)
+endif # ($(CONFIG_SOC_AMD_PHOENIX),y)

src/soc/amd/phoenix/acpi.c

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 /* TODO: See what can be made common */
 
 /* ACPI - create the Fixed ACPI Description Tables (FADT) */
@@ -53,7 +53,7 @@ unsigned long acpi_fill_madt(unsigned long current)
  */
 void acpi_fill_fadt(acpi_fadt_t *fadt)
 {
-	const struct soc_amd_morgana_config *cfg = config_of_soc();
+	const struct soc_amd_phoenix_config *cfg = config_of_soc();
 
 	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
 

src/soc/amd/phoenix/acpi/globalnvs.asl

@@ -4,7 +4,7 @@
 
 /*
  * NOTE: The layout of the GNVS structure below must match the layout in
- * soc/amd/morgana/include/soc/nvs.h !!!
+ * soc/amd/phoenix/include/soc/nvs.h !!!
  */
 
 Field (GNVS, ByteAcc, NoLock, Preserve)

src/soc/amd/phoenix/acpi/mmio.asl

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
 #include <soc/amd/common/acpi/aoac.asl>
 #include <soc/aoac_defs.h>

src/soc/amd/phoenix/acpi/pci0.asl

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
 Device(PCI0) {
 	Name(_HID, EISAID("PNP0A08"))	/* PCI Express Root Bridge */

src/soc/amd/phoenix/acpi/pci_int_defs.asl

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
 /* PCI IRQ mapping registers, C00h-C01h. */
 OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002)

src/soc/amd/phoenix/acpi/soc.asl

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
 #include "globalnvs.asl"
 

src/soc/amd/phoenix/chip.c

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
 #include <amdblocks/data_fabric.h>
 #include <console/console.h>
@@ -14,7 +14,7 @@
 #include <types.h>
 #include "chip.h"
 
-struct device_operations morgana_cpu_bus_ops = {
+struct device_operations phoenix_cpu_bus_ops = {
 	.read_resources	= noop_read_resources,
 	.set_resources	= noop_set_resources,
 	.init		= mp_cpu_bus_init,
@@ -34,7 +34,7 @@ static const char *soc_acpi_name(const struct device *dev)
 	return NULL;
 };
 
-struct device_operations morgana_pci_domain_ops = {
+struct device_operations phoenix_pci_domain_ops = {
 	.read_resources	= pci_domain_read_resources,
 	.set_resources	= pci_domain_set_resources,
 	.scan_bus	= pci_domain_scan_bus,
@@ -57,8 +57,8 @@ static void soc_final(void *chip_info)
 	fch_final(chip_info);
 }
 
-struct chip_operations soc_amd_morgana_ops = {
-	CHIP_NAME("AMD Morgana SoC")
+struct chip_operations soc_amd_phoenix_ops = {
+	CHIP_NAME("AMD Phoenix SoC")
 	.init = soc_init,
 	.final = soc_final
 };

src/soc/amd/phoenix/chip.h

@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
-#ifndef MORGANA_CHIP_H
-#define MORGANA_CHIP_H
+#ifndef PHOENIX_CHIP_H
+#define PHOENIX_CHIP_H
 
 #include <amdblocks/chip.h>
 #include <amdblocks/i2c.h>
@@ -13,9 +13,9 @@
 #include <soc/southbridge.h>
 #include <drivers/i2c/designware/dw_i2c.h>
 #include <types.h>
-#include <vendorcode/amd/fsp/morgana/FspUsb.h>
+#include <vendorcode/amd/fsp/phoenix/FspUsb.h>
 
-struct soc_amd_morgana_config {
+struct soc_amd_phoenix_config {
 	struct soc_amd_common_config common_config;
 	u8 i2c_scl_reset;
 	struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
@@ -107,4 +107,4 @@ struct soc_amd_morgana_config {
 	struct usb_phy_config usb_phy;
 };
 
-#endif /* MORGANA_CHIP_H */
+#endif /* PHOENIX_CHIP_H */

src/soc/amd/phoenix/chipset.cb

@@ -1,12 +1,12 @@
-# TODO: Update for Morgana
+# TODO: Update for Phoenix
 
-chip soc/amd/morgana
+chip soc/amd/phoenix
 	device cpu_cluster 0 on
-		ops morgana_cpu_bus_ops
+		ops phoenix_cpu_bus_ops
 	end
 	device domain 0 on
-		ops morgana_pci_domain_ops
-		device pci 00.0 alias gnb on ops morgana_root_complex_operations end
+		ops phoenix_pci_domain_ops
+		device pci 00.0 alias gnb on ops phoenix_root_complex_operations end
 		device pci 00.2 alias iommu off ops amd_iommu_ops end
 
 		device pci 01.0 on end # Dummy Host Bridge

src/soc/amd/phoenix/config.c

@@ -6,6 +6,6 @@
 
 const struct soc_amd_common_config *soc_get_common_config(void)
 {
-	const struct soc_amd_morgana_config *cfg = config_of_soc();
+	const struct soc_amd_phoenix_config *cfg = config_of_soc();
 	return &cfg->common_config;
 }

src/soc/amd/phoenix/cpu.c

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
 #include <acpi/acpi.h>
 #include <amdblocks/cpu.h>
@@ -50,7 +50,7 @@ static struct device_operations cpu_dev_ops = {
 };
 
 static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_AMD, MORGANA_A0_CPUID}, /* TODO: Update for Morgana */
+	{ X86_VENDOR_AMD, PHOENIX_A0_CPUID}, /* TODO: Update for Phoenix */
 	{ 0, 0 },
 };
 

src/soc/amd/phoenix/early_fch.c

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/aoac.h>

src/soc/amd/phoenix/espi_util.c

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
 #include <amdblocks/spi.h>
 #include <soc/espi.h>

src/soc/amd/phoenix/fch.c

@@ -124,7 +124,7 @@ static void fch_init_acpi_ports(void)
 /* configure the general purpose PCIe clock outputs according to the devicetree settings */
 static void gpp_clk_setup(void)
 {
-	struct soc_amd_morgana_config *cfg = config_of_soc();
+	struct soc_amd_phoenix_config *cfg = config_of_soc();
 
 	/* look-up table to be able to iterate over the PCIe clock output settings */
 	const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = {

src/soc/amd/phoenix/fsp_m_params.c

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 /* TODO: See what can be moved to common */
 
 #include <amdblocks/apob_cache.h>
@@ -15,7 +15,7 @@
 #include <soc/pci_devs.h>
 #include <string.h>
 #include <types.h>
-#include <vendorcode/amd/fsp/morgana/FspUsb.h>
+#include <vendorcode/amd/fsp/phoenix/FspUsb.h>
 #include "chip.h"
 
 __weak void mb_pre_fspm(FSP_M_CONFIG *mcfg)
@@ -71,7 +71,7 @@ static void fsp_assign_ioapic_upds(FSP_M_CONFIG *mcfg)
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
 	FSP_M_CONFIG *mcfg = &mupd->FspmConfig;
-	const struct soc_amd_morgana_config *config = config_of_soc();
+	const struct soc_amd_phoenix_config *config = config_of_soc();
 
 	mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache();
 

src/soc/amd/phoenix/fsp_s_params.c

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
 #include <acpi/acpi.h>
 #include <amdblocks/apob_cache.h>

src/soc/amd/phoenix/i2c.c

@@ -42,7 +42,7 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar)
 
 void reset_i2c_peripherals(void)
 {
-	const struct soc_amd_morgana_config *cfg = config_of_soc();
+	const struct soc_amd_phoenix_config *cfg = config_of_soc();
 	struct soc_i2c_peripheral_reset_info reset_info;
 
 	reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
@@ -53,7 +53,7 @@ void reset_i2c_peripherals(void)
 
 void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
 {
-	const struct soc_amd_morgana_config *config = config_of_soc();
+	const struct soc_amd_phoenix_config *config = config_of_soc();
 
 	if (bus >= ARRAY_SIZE(config->i2c_pad))
 		return;
@@ -69,7 +69,7 @@ const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)
 
 const struct dw_i2c_bus_config *soc_get_i2c_bus_config(size_t *num_buses)
 {
-	const struct soc_amd_morgana_config *config = config_of_soc();
+	const struct soc_amd_phoenix_config *config = config_of_soc();
 
 	*num_buses = ARRAY_SIZE(config->i2c);
 	return config->i2c;

src/soc/amd/phoenix/include/soc/acpi.h

@@ -2,8 +2,8 @@
 
 /* TODO: Move to common */
 
-#ifndef AMD_MORGANA_ACPI_H
-#define AMD_MORGANA_ACPI_H
+#ifndef AMD_PHOENIX_ACPI_H
+#define AMD_PHOENIX_ACPI_H
 
 #include <acpi/acpi.h>
 #include <amdblocks/acpi.h>
@@ -20,4 +20,4 @@
 uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current,
 				  acpi_rsdp_t *rsdp);
 
-#endif /* AMD_MORGANA_ACPI_H */
+#endif /* AMD_PHOENIX_ACPI_H */

src/soc/amd/phoenix/include/soc/amd_pci_int_defs.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_MORGANA_AMD_PCI_INT_DEFS_H
-#define AMD_MORGANA_AMD_PCI_INT_DEFS_H
+#ifndef AMD_PHOENIX_AMD_PCI_INT_DEFS_H
+#define AMD_PHOENIX_AMD_PCI_INT_DEFS_H
 
 /*
  * PIRQ and device routing - these define the index into the
@@ -53,4 +53,4 @@
 #define PIRQ_UART2	0x78	/* UART2 */
 #define PIRQ_UART3	0x79	/* UART3 */
 
-#endif /* AMD_MORGANA_AMD_PCI_INT_DEFS_H */
+#endif /* AMD_PHOENIX_AMD_PCI_INT_DEFS_H */

src/soc/amd/phoenix/include/soc/aoac_defs.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_MORGANA_AOAC_DEFS_H
-#define AMD_MORGANA_AOAC_DEFS_H
+#ifndef AMD_PHOENIX_AOAC_DEFS_H
+#define AMD_PHOENIX_AOAC_DEFS_H
 
 /* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */
 #define FCH_AOAC_DEV_CLK_GEN		0
@@ -20,4 +20,4 @@
 #define FCH_AOAC_DEV_ESPI		27
 #define FCH_AOAC_DEV_EMMC		28
 
-#endif /* AMD_MORGANA_AOAC_DEFS_H */
+#endif /* AMD_PHOENIX_AOAC_DEFS_H */

src/soc/amd/phoenix/include/soc/cpu.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_PHOENIX_CPU_H
+#define AMD_PHOENIX_CPU_H
+
+#define PHOENIX_A0_CPUID	0x00a70f80
+
+#endif /* AMD_PHOENIX_CPU_H */

src/soc/amd/phoenix/include/soc/data_fabric.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_MORGANA_DATA_FABRIC_H
-#define AMD_MORGANA_DATA_FABRIC_H
+#ifndef AMD_PHOENIX_DATA_FABRIC_H
+#define AMD_PHOENIX_DATA_FABRIC_H
 
 #include <types.h>
 
@@ -45,4 +45,4 @@ union df_ficaa {
 	uint32_t raw;
 };
 
-#endif /* AMD_MORGANA_DATA_FABRIC_H */
+#endif /* AMD_PHOENIX_DATA_FABRIC_H */

src/soc/amd/phoenix/include/soc/espi.h

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* TODO: Update for Phoenix */
+
+#ifndef AMD_PHOENIX_ESPI_H
+#define AMD_PHOENIX_ESPI_H
+
+void espi_switch_to_spi1_pads(void);
+
+#endif /* AMD_PHOENIX_ESPI_H */

src/soc/amd/phoenix/include/soc/gpio.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_MORGANA_GPIO_H
-#define AMD_MORGANA_GPIO_H
+#ifndef AMD_PHOENIX_GPIO_H
+#define AMD_PHOENIX_GPIO_H
 
 #define GPIO_DEVICE_NAME	"AMD0030"
 #define GPIO_DEVICE_DESC	"GPIO Controller"
@@ -296,4 +296,4 @@
 #define GPIO_157_IOMUX_GPIOxx 0
 #define GPIO_157_IOMUX_UART4_INTR 1
 
-#endif /* AMD_MORGANA_GPIO_H */
+#endif /* AMD_PHOENIX_GPIO_H */

src/soc/amd/phoenix/include/soc/i2c.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_MORGANA_I2C_H
-#define AMD_MORGANA_I2C_H
+#ifndef AMD_PHOENIX_I2C_H
+#define AMD_PHOENIX_I2C_H
 
 #include <soc/gpio.h>
 #include <types.h>
@@ -27,4 +27,4 @@
 void i2c_set_bar(unsigned int bus, uintptr_t bar);
 void reset_i2c_peripherals(void);
 
-#endif /* AMD_MORGANA_I2C_H */
+#endif /* AMD_PHOENIX_I2C_H */

src/soc/amd/phoenix/include/soc/iomap.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_MORGANA_IOMAP_H
-#define AMD_MORGANA_IOMAP_H
+#ifndef AMD_PHOENIX_IOMAP_H
+#define AMD_PHOENIX_IOMAP_H
 
 #define I2C_MASTER_DEV_COUNT		4
 #define I2C_MASTER_START_INDEX		0
@@ -54,4 +54,4 @@
 #define   ACPI_GPE0_EN			(ACPI_GPE0_BLK + 0x04)
 #define SMB_BASE_ADDR			0x0b00
 
-#endif /* AMD_MORGANA_IOMAP_H */
+#endif /* AMD_PHOENIX_IOMAP_H */

src/soc/amd/phoenix/include/soc/lpc.h

@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
-#ifndef AMD_MORGANA_LPC_H
-#define AMD_MORGANA_LPC_H
+#ifndef AMD_PHOENIX_LPC_H
+#define AMD_PHOENIX_LPC_H
 
 /* LPC_MISC_CONTROL_BITS at D14F3x078 */
 
@@ -20,4 +20,4 @@
 #define   SPI_ROM_ALT_ENABLE		BIT(0)
 #define   SPI_PRESERVE_BITS		(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4))
 
-#endif /* AMD_MORGANA_LPC_H */
+#endif /* AMD_PHOENIX_LPC_H */

src/soc/amd/phoenix/include/soc/msr.h

@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
-#ifndef AMD_MORGANA_MSR_H
-#define AMD_MORGANA_MSR_H
+#ifndef AMD_PHOENIX_MSR_H
+#define AMD_PHOENIX_MSR_H
 
 /* MSRC001_00[6B:64] P-state [7:0] bit definitions */
 #define PSTATE_DEF_HI_ENABLE_SHIFT	31
@@ -45,4 +45,4 @@
 #define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe7
 #define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe8
 
-#endif /* AMD_MORGANA_MSR_H */
+#endif /* AMD_PHOENIX_MSR_H */

src/soc/amd/phoenix/include/soc/nvs.h

@@ -1,15 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
 /*
  * NOTE: The layout of the global_nvs structure below must match the layout
- * in soc/soc/amd/morgana/acpi/globalnvs.asl !!!
+ * in soc/soc/amd/phoenix/acpi/globalnvs.asl !!!
  *
  */
 
-#ifndef AMD_MORGANA_NVS_H
-#define AMD_MORGANA_NVS_H
+#ifndef AMD_PHOENIX_NVS_H
+#define AMD_PHOENIX_NVS_H
 
 #include <stdint.h>
 
@@ -26,4 +26,4 @@ struct __packed global_nvs {
 	uint8_t		tpsv; /* 0x19 - Passive Threshold */
 };
 
-#endif /* AMD_MORGANA_NVS_H */
+#endif /* AMD_PHOENIX_NVS_H */

src/soc/amd/phoenix/include/soc/pci_devs.h

@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
-#ifndef AMD_MORGANA_PCI_DEVS_H
-#define AMD_MORGANA_PCI_DEVS_H
+#ifndef AMD_PHOENIX_PCI_DEVS_H
+#define AMD_PHOENIX_PCI_DEVS_H
 
 #include <device/pci_def.h>
 #include <amdblocks/pci_devs.h>
@@ -132,4 +132,4 @@
 #define DF_F7_DEVFN		PCI_DEVFN(DF_DEV, 7)
 #define SOC_DF_F7_DEV		_SOC_DEV(DF_DEV, 7)
 
-#endif /* AMD_MORGANA_PCI_DEVS_H */
+#endif /* AMD_PHOENIX_PCI_DEVS_H */

src/soc/amd/phoenix/include/soc/platform_descriptors.h

@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
-#ifndef AMD_MORGANA_PLATFORM_DESCRIPTORS_H
-#define AMD_MORGANA_PLATFORM_DESCRIPTORS_H
+#ifndef AMD_PHOENIX_PLATFORM_DESCRIPTORS_H
+#define AMD_PHOENIX_PLATFORM_DESCRIPTORS_H
 
 #include <types.h>
 #include <platform_descriptors.h>
@@ -16,4 +16,4 @@ void mainboard_get_dxio_ddi_descriptors(
 
 void mb_pre_fspm(FSP_M_CONFIG *mcfg);
 
-#endif /* AMD_MORGANA_PLATFORM_DESCRIPTORS_H */
+#endif /* AMD_PHOENIX_PLATFORM_DESCRIPTORS_H */

src/soc/amd/phoenix/include/soc/psp_transfer.h

@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
-#ifndef AMD_MORGANA_PSP_TRANSFER_H
-#define AMD_MORGANA_PSP_TRANSFER_H
+#ifndef AMD_PHOENIX_PSP_TRANSFER_H
+#define AMD_PHOENIX_PSP_TRANSFER_H
 
 # if (CONFIG_CMOS_RECOVERY_BYTE != 0)
 #  define CMOS_RECOVERY_BYTE CONFIG_CMOS_RECOVERY_BYTE
@@ -61,4 +61,4 @@ void replay_transfer_buffer_cbmemc(void);
 void boot_with_psp_timestamp(uint64_t base_timestamp);
 
 #endif
-#endif	/* AMD_MORGANA_PSP_TRANSFER_H */
+#endif	/* AMD_PHOENIX_PSP_TRANSFER_H */

src/soc/amd/phoenix/include/soc/psp_verstage_addr.h

@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
-#ifndef AMD_MORGANA_PSP_VERSTAGE_ADDR_H
-#define AMD_MORGANA_PSP_VERSTAGE_ADDR_H
+#ifndef AMD_PHOENIX_PSP_VERSTAGE_ADDR_H
+#define AMD_PHOENIX_PSP_VERSTAGE_ADDR_H
 
 /*
  * Start of available space is 0x0 and this is where the
@@ -22,4 +22,4 @@
 #define PSP_VERSTAGE_STACK_START	0x2a000
 #define PSP_VERSTAGE_STACK_SIZE		(40K)
 
-#endif  /* AMD_MORGANA_PSP_VERSTAGE_ADDR_H */
+#endif  /* AMD_PHOENIX_PSP_VERSTAGE_ADDR_H */

src/soc/amd/phoenix/include/soc/smi.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#ifndef AMD_MORGANA_SMI_H
-#define AMD_MORGANA_SMI_H
+#ifndef AMD_PHOENIX_SMI_H
+#define AMD_PHOENIX_SMI_H
 
 #include <types.h>
 
@@ -179,4 +179,4 @@
 
 #define SMI_MODE_MASK			0x03
 
-#endif /* AMD_MORGANA_SMI_H */
+#endif /* AMD_PHOENIX_SMI_H */

src/soc/amd/phoenix/include/soc/smu.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_MORGANA_SMU_H
-#define AMD_MORGANA_SMU_H
+#ifndef AMD_PHOENIX_SMU_H
+#define AMD_PHOENIX_SMU_H
 
 /* SMU mailbox register offsets in SMN */
 #define SMN_SMU_MESG_ID		0x3b10528
@@ -20,4 +20,4 @@ enum smu_message_id {
  */
 void smu_sx_entry(void);
 
-#endif /* AMD_MORGANA_SMU_H */
+#endif /* AMD_PHOENIX_SMU_H */

src/soc/amd/phoenix/include/soc/southbridge.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_MORGANA_SOUTHBRIDGE_H
-#define AMD_MORGANA_SOUTHBRIDGE_H
+#ifndef AMD_PHOENIX_SOUTHBRIDGE_H
+#define AMD_PHOENIX_SOUTHBRIDGE_H
 
 #include <soc/iomap.h>
 
@@ -118,4 +118,4 @@ void fch_early_init(void);
 void fch_init(void *chip_info);
 void fch_final(void *chip_info);
 
-#endif /* AMD_MORGANA_SOUTHBRIDGE_H */
+#endif /* AMD_PHOENIX_SOUTHBRIDGE_H */

src/soc/amd/phoenix/include/soc/uart.h

@@ -1,12 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
-#ifndef AMD_MORGANA_UART_H
-#define AMD_MORGANA_UART_H
+#ifndef AMD_PHOENIX_UART_H
+#define AMD_PHOENIX_UART_H
 
 #include <types.h>
 
 void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */
 
-#endif /* AMD_MORGANA_UART_H */
+#endif /* AMD_PHOENIX_UART_H */

src/soc/amd/phoenix/psp_verstage/Makefile.inc

@@ -4,9 +4,9 @@ ifeq $($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y)
 
 subdirs-y += ../../common/psp_verstage
 
-verstage-generic-ccopts += -I$(src)/soc/amd/morgana/psp_verstage/include
+verstage-generic-ccopts += -I$(src)/soc/amd/phoenix/psp_verstage/include
 verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include
-verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/morgana/include
+verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/phoenix/include
 verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/common/include
 
 verstage-y += svc.c

src/soc/amd/phoenix/psp_verstage/chipset.c

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
 #include <bl_uapp/bl_syscall_public.h>
 #include <cbfs.h>

src/soc/amd/phoenix/psp_verstage/svc.c

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
 #include "svc.h"
 

src/soc/amd/phoenix/psp_verstage/svc.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 /* TODO: See what can be made common */
 
 #ifndef PSP_VERSTAGE_SVC_H

src/soc/amd/phoenix/root_complex.c

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
 #include <acpi/acpigen.h>
 #include <amdblocks/acpi.h>
@@ -191,7 +191,7 @@ static void root_complex_init(struct device *dev)
 
 static void acipgen_dptci(void)
 {
-	const struct soc_amd_morgana_config *config = config_of_soc();
+	const struct soc_amd_phoenix_config *config = config_of_soc();
 
 	/* Normal mode DPTC values. */
 	struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC,
@@ -228,7 +228,7 @@ static const char *gnb_acpi_name(const struct device *dev)
 	return "GNB";
 }
 
-struct device_operations morgana_root_complex_operations = {
+struct device_operations phoenix_root_complex_operations = {
 	.read_resources		= read_resources,
 	.set_resources		= noop_set_resources,
 	.enable_resources	= pci_dev_enable_resources,

src/soc/amd/phoenix/smihandler.c

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
 #include <acpi/acpi.h>
 #include <amdblocks/acpi.h>

src/soc/amd/phoenix/xhci.c

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
 #include <amdblocks/gpio.h>
 #include <amdblocks/smi.h>

src/vendorcode/amd/fsp/phoenix/FspUsb.h

@@ -1,7 +1,7 @@
 #ifndef __FSPUSB_H__
 #define __FSPUSB_H__
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
 #include <FspUpd.h>
 

src/vendorcode/amd/fsp/phoenix/FspmUpd.h

@@ -4,7 +4,7 @@
  *
  */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
 #ifndef __FSPMUPD_H__
 #define __FSPMUPD_H__

src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_syscall_public.h

@@ -27,7 +27,7 @@
  *
  ***************************************************************************/
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
 #ifndef _BL_SYSCALL_PUBLIC_H_
 #define _BL_SYSCALL_PUBLIC_H_

src/vendorcode/amd/fsp/phoenix/platform_descriptors.h

@@ -5,7 +5,7 @@
  * connector types connected to the SOC.
  */
 
-/* TODO: Update for Morgana */
+/* TODO: Update for Phoenix */
 
 #ifndef PI_PLATFORM_DESCRIPTORS_H
 #define PI_PLATFORM_DESCRIPTORS_H
@@ -164,11 +164,11 @@ typedef struct __packed {
 } fsp_ddi_descriptor;
 
 /*
- * Morgana DXIO Descriptor: Used for assigning lanes to PCIe engines, configure
+ * Phoenix DXIO Descriptor: Used for assigning lanes to PCIe engines, configure
  * bifurcation and other settings. Beware that the lane numbers in here are the
  * logical and not the physical lane numbers!
  *
- * Morgana DXIO logical lane to physical PCIe lane mapping:
+ * Phoenix DXIO logical lane to physical PCIe lane mapping:
  *
  *   logical | physical
  * ----------|------------

util/amdfwtool/amdfwtool.c

@@ -207,7 +207,7 @@ static void usage(void)
 	printf("                               area\n");
 	printf("--soc-name <socname>           Specify SOC name. Supported names are\n");
 	printf("                               Stoneyridge, Raven, Picasso, Renoir, Cezanne\n");
-	printf("                               Mendocino, Morgana, Glinda, or Lucienne\n");
+	printf("                               Mendocino, Phoenix, Glinda, or Lucienne\n");
 	printf("\nEmbedded Firmware Structure options used by the PSP:\n");
 	printf("--spi-speed <HEX_VAL>          SPI fast speed to place in EFS Table\n");
 	printf("                               0x0 66.66Mhz\n");
@@ -654,7 +654,7 @@ enum platform {
 	PLATFORM_CEZANNE,
 	PLATFORM_MENDOCINO,
 	PLATFORM_LUCIENNE,
-	PLATFORM_MORGANA,
+	PLATFORM_PHOENIX,
 	PLATFORM_GLINDA
 };
 
@@ -1937,8 +1937,8 @@ static int set_efs_table(uint8_t soc_id, amd_cb_config *cb_config,
 			return 1;
 		}
 		break;
-	/* TODO: Update for morgana and glinda */
-	case PLATFORM_MORGANA:
+	/* TODO: Update for phoenix and glinda */
+	case PLATFORM_PHOENIX:
 	case PLATFORM_GLINDA:
 		break;
 	case PLATFORM_UNKNOWN:
@@ -2013,8 +2013,8 @@ static int identify_platform(char *soc_name)
 		return PLATFORM_RENOIR;
 	else if (!strcasecmp(soc_name, "Lucienne"))
 		return PLATFORM_LUCIENNE;
-	else if (!strcasecmp(soc_name, "Morgana"))
-		return PLATFORM_MORGANA;
+	else if (!strcasecmp(soc_name, "Phoenix"))
+		return PLATFORM_PHOENIX;
 	else if (!strcasecmp(soc_name, "Glinda"))
 		return PLATFORM_GLINDA;
 	else