mb/google/brya/agah: Adjust i2c1 and i2c2 timing Parameters for 400KHz

Adjust timing parameters on i2c1 and i2c2 to meet timing requirements.

For SCL, the t-high time is now over the min 600ns requirement
for 400KHz operation (measure at over 700ns). Also, this change
does not violate other parameters - rise time, setup time and hold time.

BUG=b:264704732
TEST=Verified all timings meet spec now

Change-Id: I0e92b2c9c25e7fb5fa7082af3f4a88da168c3ef2
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

src/mainboard/google/brya/variants/agah/overridetree.cb

@@ -20,9 +20,15 @@ chip soc/intel/alderlake
 		},
 		.i2c[1] = {
 			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 650,
+			.fall_time_ns = 300,
+			.data_hold_time_ns = 50,
 		},
 		.i2c[2] = {
 			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 650,
+			.fall_time_ns = 300,
+			.data_hold_time_ns = 50,
 		},
 		.i2c[3] = {
 			.early_init = 1,