diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig
index 070a3ce8c7..ee50152513 100644
--- a/src/soc/nvidia/tegra132/Kconfig
+++ b/src/soc/nvidia/tegra132/Kconfig
@@ -101,7 +101,7 @@ config MTS_DIRECTORY
 
 config TRUSTZONE_CARVEOUT_SIZE_MB
 	hex "Size of Trust Zone region"
-	default 0x1
+	default 0x4
 	help
 	  Size of Trust Zone area in MiB to reserve in memory map.
 
diff --git a/src/soc/nvidia/tegra132/mmu_operations.c b/src/soc/nvidia/tegra132/mmu_operations.c
index 5e02e07f10..1f6258f02d 100644
--- a/src/soc/nvidia/tegra132/mmu_operations.c
+++ b/src/soc/nvidia/tegra132/mmu_operations.c
@@ -84,6 +84,7 @@ void tegra132_mmu_init(void)
 {
 	uintptr_t tz_base_mib;
 	size_t tz_size_mib;
+	size_t ttb_size_mib;
 	struct memranges *map = &t132_mmap_ranges;
 
 	tegra132_memrange_init(map);
@@ -92,7 +93,7 @@ void tegra132_mmu_init(void)
 	/* Place page tables at the base of the trust zone region. */
 	carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib);
 	tz_base_mib *= MiB;
-	tz_size_mib *= MiB;
-	mmu_init(map, (void *)tz_base_mib, tz_size_mib);
+	ttb_size_mib = TTB_SIZE * MiB;
+	mmu_init(map, (void *)tz_base_mib, ttb_size_mib);
 	mmu_enable(tz_base_mib);
 }
diff --git a/src/soc/nvidia/tegra132/mmu_operations.h b/src/soc/nvidia/tegra132/mmu_operations.h
index bc2773ce21..8c82b26477 100644
--- a/src/soc/nvidia/tegra132/mmu_operations.h
+++ b/src/soc/nvidia/tegra132/mmu_operations.h
@@ -22,4 +22,7 @@
 
 void tegra132_mmu_init(void);
 
+/* Default ttb size of 1MiB */
+#define TTB_SIZE 0x1
+
 #endif //__SOC_NVIDIA_TEGRA132_MMU_OPERATIONS_H__