diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c
index ef41b7720e..ebc43de823 100644
--- a/src/mainboard/ocp/monolake/romstage.c
+++ b/src/mainboard/ocp/monolake/romstage.c
@@ -19,9 +19,6 @@
 #include <soc/romstage.h>
 #include <drivers/intel/fsp1_0/fsp_util.h>
 #include <drivers/vpd/vpd.h>
-#include <cpu/x86/msr.h>
-#include <cf9_reset.h>
-#include <console/console.h>
 #include <device/pci_ops.h>
 #include <soc/pci_devs.h>
 #include <soc/lpc.h>
@@ -193,20 +190,7 @@ static const struct gpio_config gpio_tables[] = {
  */
 void early_mainboard_romstage_entry(void)
 {
-	/*
-	 * Sometimes the system boots in an invalid state, where random values
-	 * have been written to MSRs and then the MSRs are locked.
-	 * Seems to always happen on warm reset.
-	 *
-	 * Power cycling or a board_reset() isn't sufficient in this case, so
-	 * issue a full_reset() to "fix" this issue.
-	 */
-	msr_t msr = rdmsr(IA32_FEATURE_CONTROL);
-	if (msr.lo & 1) {
-		console_init();
-		printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");
-		full_reset();
-	}
+
 }
 
 /**
diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c
index 108d7a1c4d..b1f8f26796 100644
--- a/src/mainboard/ocp/wedge100s/romstage.c
+++ b/src/mainboard/ocp/wedge100s/romstage.c
@@ -17,9 +17,6 @@
 #include <stddef.h>
 #include <soc/romstage.h>
 #include <drivers/intel/fsp1_0/fsp_util.h>
-#include <cpu/x86/msr.h>
-#include <cf9_reset.h>
-#include <console/console.h>
 #include <device/pci_ops.h>
 #include <soc/pci_devs.h>
 #include <soc/lpc.h>
@@ -44,25 +41,6 @@ void early_mainboard_romstage_entry(void)
 
 	if (CONFIG(CONSOLE_SERIAL))
 		ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
-
-	/*
-	 * Sometimes the system boots in an invalid state, where random values
-	 * have been written to MSRs and then the MSRs are locked.
-	 * Seems to always happen on warm reset.
-	 *
-	 * Power cycling or a board_reset() isn't sufficient in this case, so
-	 * issue a full_reset() to "fix" this issue.
-	 *
-	 * It seems to be a deficiency in the reset logic, as other
-	 * FSP broadwell DE boards are not affected.
-	 */
-	msr_t msr = rdmsr(IA32_FEATURE_CONTROL);
-	if (msr.lo & 1) {
-		console_init();
-		printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");
-		full_reset();
-	}
 }
 
 /**
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
index 9699927574..dbf4bc3482 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
@@ -21,8 +21,10 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <console/usb.h>
+#include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
+#include <cf9_reset.h>
 #include <program_loading.h>
 #include <timestamp.h>
 #include <version.h>
@@ -125,7 +127,24 @@ static void early_iio_hide(void)
 			iio_hide(dev);
 		}
 	}
+}
 
+static void check_msr_lock(void)
+{
+	/*
+	 * Sometimes the system boots in an invalid state, where random values
+	 * have been written to MSRs and then the MSRs are locked.
+	 * Seems to always happen on warm reset.
+	 *
+	 * Power cycling or a board_reset() isn't sufficient in this case, so
+	 * issue a full_reset() to "fix" this issue.
+	 */
+	msr_t msr = rdmsr(IA32_FEATURE_CONTROL);
+	if (msr.lo & 1) {
+		console_init();
+		printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");
+		full_reset();
+	}
 }
 
 /* Entry from cache-as-ram.inc. */
@@ -146,6 +165,8 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
 		enable_integrated_uart(CONFIG_UART_FOR_CONSOLE);
 	}
 
+	check_msr_lock();
+
 	/* Call into mainboard. */
 	post_code(0x41);
 	early_mainboard_romstage_entry();