nb/intel/sandybridge: Refactor `get_pcie_bar`
Turn it into `decode_pcie_bar`, taken from gm45. Change-Id: Id1c2cfbcac1a798d046beced790930511dc97972 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44121 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -2,6 +2,7 @@
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#include <console/console.h>
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#include <acpi/acpi.h>
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#include <commonlib/helpers.h>
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#include <device/pci_ops.h>
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#include <stdint.h>
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#include <delay.h>
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@ -39,18 +40,16 @@ int bridge_silicon_revision(void)
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static const int legacy_hole_base_k = 0xa0000 / 1024;
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static const int legacy_hole_size_k = 384;
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static int get_pcie_bar(u32 *base)
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static int decode_pcie_bar(u32 *const base, u32 *const len)
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{
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struct device *dev;
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u32 pciexbar_reg;
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*base = 0;
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*len = 0;
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dev = pcidev_on_root(0, 0);
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struct device *dev = pcidev_on_root(0, 0);
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if (!dev)
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return 0;
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pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
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const u32 pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
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/* MMCFG not supported or not enabled */
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if (!(pciexbar_reg & (1 << 0)))
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@ -58,14 +57,17 @@ static int get_pcie_bar(u32 *base)
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switch ((pciexbar_reg >> 1) & 3) {
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case 0: /* 256MB */
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*base = pciexbar_reg & (0xffffffffULL << 28);
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return 256;
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*base = pciexbar_reg & (0x0f << 28);
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*len = 256 * MiB;
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return 1;
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case 1: /* 128M */
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*base = pciexbar_reg & (0xffffffffULL << 27);
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return 128;
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*base = pciexbar_reg & (0x1f << 27);
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*len = 128 * MiB;
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return 1;
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case 2: /* 64M */
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*base = pciexbar_reg & (0xffffffffULL << 26);
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return 64;
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*base = pciexbar_reg & (0x3f << 26);
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*len = 64 * MiB;
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return 1;
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}
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return 0;
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@ -129,8 +131,7 @@ static void add_fixed_resources(struct device *dev, int index)
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static void mc_read_resources(struct device *dev)
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{
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u32 pcie_config_base;
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int buses;
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u32 pcie_config_base, pcie_config_len;
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uint64_t tom, me_base, touud;
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uint32_t tseg_base, uma_size, tolud;
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uint16_t ggc;
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@ -139,8 +140,8 @@ static void mc_read_resources(struct device *dev)
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pci_dev_read_resources(dev);
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buses = get_pcie_bar(&pcie_config_base);
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if (buses) {
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if (decode_pcie_bar(&pcie_config_base, &pcie_config_len)) {
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const int buses = pcie_config_len / MiB;
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struct resource *resource = new_resource(dev, PCIEXBAR);
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mmconf_resource_init(resource, pcie_config_base, buses);
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}
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