AMD K8 fam10: Add ht_route_link()
Change-Id: I41aeb80121f120641b65759c8502150ce89caa30 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8556 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
This commit is contained in:
Kyösti Mälkki
parent
59d609217b
commit
20968c9220
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@ -158,6 +158,37 @@ static bool is_non_coherent_link(struct device *dev, struct bus *link)
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return !!(link_type & NonCoherent);
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}
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typedef enum {
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HT_ROUTE_CLOSE,
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HT_ROUTE_SCAN,
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HT_ROUTE_FINAL,
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} scan_state;
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static void ht_route_link(struct bus *link, scan_state mode)
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{
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struct bus *parent = link->dev->bus;
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u32 busses;
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/* Configure the bus numbers for this bridge: the configuration
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* transactions will not be propagated by the bridge if it is
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* not correctly configured
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*/
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busses = pci_read_config32(link->dev, link->cap + 0x14);
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busses &= 0xff000000;
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busses |= parent->secondary & 0xff;
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if (mode == HT_ROUTE_CLOSE) {
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busses |= 0xfeff << 8;
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} else if (mode == HT_ROUTE_SCAN) {
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busses |= ((u32) link->secondary & 0xff) << 8;
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busses |= 0xfc << 16;
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} else if (mode == HT_ROUTE_FINAL) {
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busses |= ((u32) link->secondary & 0xff) << 8;
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busses |= ((u32) link->subordinate & 0xff) << 16;
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}
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pci_write_config32(link->dev, link->cap + 0x14, busses);
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}
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static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_sblink,
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u32 max)
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{
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@ -170,7 +201,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
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u32 ht_unitid_base[4]; // here assume only 4 HT device on chain
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u32 max_bus;
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u32 min_bus;
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u32 busses;
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#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1
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u32 busn = max&0xff;
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#endif
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@ -219,23 +249,11 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
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link->secondary = min_bus;
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link->subordinate = link->secondary;
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/* Read the existing primary/secondary/subordinate bus
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* number configuration.
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*/
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busses = pci_read_config32(dev, link->cap + 0x14);
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/* Configure the bus numbers for this bridge: the configuration
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* transactions will not be propagates by the bridge if it is
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* not correctly configured
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*/
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busses &= 0xffff00ff;
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busses |= ((u32)(link->secondary) << 8);
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pci_write_config32(dev, link->cap + 0x14, busses);
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ht_route_link(link, HT_ROUTE_SCAN);
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/* set the config map space */
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set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, max_bus, sysconf.segbit, sysconf.nodes);
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set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes);
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/* Now we can scan all of the subordinate busses i.e. the
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* chain on the hypertranport link
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@ -255,6 +273,8 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
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/* Now that nothing is overlapping it is safe to scan the children. */
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pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7);
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ht_route_link(link, HT_ROUTE_FINAL);
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/* We know the number of busses behind this bridge. Set the
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* subordinate bus number to it's real value
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*/
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@ -96,6 +96,38 @@ static bool is_non_coherent_link(struct device *dev, struct bus *link)
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return !!(link_type & NonCoherent);
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}
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typedef enum {
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HT_ROUTE_CLOSE,
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HT_ROUTE_SCAN,
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HT_ROUTE_FINAL,
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} scan_state;
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static void ht_route_link(struct bus *link, scan_state mode)
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{
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struct device *dev = link->dev;
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struct bus *parent = dev->bus;
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u32 busses;
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/* Configure the bus numbers for this bridge: the configuration
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* transactions will not be propagated by the bridge if it is
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* not correctly configured
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*/
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busses = pci_read_config32(link->dev, link->cap + 0x14);
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busses &= 0xff000000;
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busses |= parent->secondary & 0xff;
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if (mode == HT_ROUTE_CLOSE) {
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busses |= 0xfeff << 8;
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} else if (mode == HT_ROUTE_SCAN) {
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busses |= ((u32) link->secondary & 0xff) << 8;
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busses |= 0xff << 16;
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} else if (mode == HT_ROUTE_FINAL) {
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busses |= ((u32) link->secondary & 0xff) << 8;
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busses |= ((u32) link->subordinate & 0xff) << 16;
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}
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pci_write_config32(link->dev, link->cap + 0x14, busses);
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}
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static u32 amdk8_nodeid(device_t dev)
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{
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return (dev->path.pci.devfn >> 3) - 0x18;
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@ -106,10 +138,9 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_
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{
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int i;
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unsigned int next_unitid;
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u32 busses, config_busses;
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u32 config_busses;
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u32 free_reg, config_reg;
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u32 ht_unitid_base[4]; // here assume only 4 HT device on chain
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u32 max_bus;
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u32 min_bus;
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u32 max_devfn;
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@ -168,34 +199,20 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_
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#else
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min_bus = ++max;
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#endif
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max_bus = 0xff;
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link->secondary = min_bus;
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link->subordinate = link->secondary;
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/* Read the existing primary/secondary/subordinate bus
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* number configuration.
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*/
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busses = pci_read_config32(dev, link->cap + 0x14);
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ht_route_link(link, HT_ROUTE_SCAN);
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config_busses = f1_read_config32(config_reg);
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/* Configure the bus numbers for this bridge: the configuration
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* transactions will not be propagates by the bridge if it is
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* not correctly configured
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*/
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busses &= 0xff000000;
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busses |= (((unsigned int)(dev->bus->secondary) << 0) |
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((unsigned int)(link->secondary) << 8) |
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(max_bus << 16));
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pci_write_config32(dev, link->cap + 0x14, busses);
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config_busses &= 0x000fc88;
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config_busses |=
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(3 << 0) | /* rw enable, no device compare */
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(( nodeid & 7) << 4) |
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((link->link_num & 3) << 8) |
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((link->secondary) << 16) |
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(max_bus << 24);
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(0xff << 24);
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f1_write_config32(config_reg, config_busses);
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/* Now we can scan all of the subordinate busses i.e. the
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@ -218,9 +235,8 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_
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/* We know the number of busses behind this bridge. Set the
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* subordinate bus number to it's real value
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*/
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busses = (busses & 0xff00ffff) |
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((unsigned int) (link->subordinate) << 16);
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pci_write_config32(dev, link->cap + 0x14, busses);
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ht_route_link(link, HT_ROUTE_FINAL);
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config_busses = (config_busses & 0x00ffffff) |
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(link->subordinate << 24);
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