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libpayload/pci: Add pci_map_bus function for MediaTek platform 

Add 'pci_map_bus' function and PCIE_MEDIATEK config for MediaTek
platform.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Jianjun Wang 2021-07-28 16:53:43 +08:00 committed by Yu-Ping Wu
parent 2ad74deb2a
commit 20a87c0bed
3 changed files with 27 additions and 0 deletions
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5
payloads/libpayload/Kconfig
View File

@ -413,6 +413,11 @@ config PCI_IO_OPS
default y if ARCH_X86
default n
config PCIE_MEDIATEK
bool "Support for PCIe devices on MediaTek platforms"
depends on PCI && !PCI_IO_OPS
default n
config NVRAM
bool "Support for reading/writing NVRAM bytes"
depends on ARCH_X86 # for now

2
payloads/libpayload/drivers/Makefile.inc
View File

@ -36,6 +36,8 @@ else
libc-$(CONFIG_LP_PCI) += pci_map_bus_ops.c
endif
libc-$(CONFIG_LP_PCIE_MEDIATEK) += pcie_mediatek.c
libc-$(CONFIG_LP_SPEAKER) += speaker.c
libc-$(CONFIG_LP_8250_SERIAL_CONSOLE) += serial/8250.c serial/serial.c

20
payloads/libpayload/drivers/pcie_mediatek.c Normal file
View File

@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <libpayload.h>
#include <pci.h>
#define PCIE_CFGNUM_REG 0x140
#define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0))
#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8))
#define PCIE_CFG_OFFSET_ADDR 0x1000
#define PCIE_CFG_HEADER(bus, devfn) \
(PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))
uintptr_t pci_map_bus(pcidev_t dev)
{
u32 devfn = (PCI_SLOT(dev) << 3) | PCI_FUNC(dev);
u32 val = PCIE_CFG_HEADER(PCI_BUS(dev), devfn);
write32((void *)(lib_sysinfo.pcie_ctrl_base + PCIE_CFGNUM_REG), val);
return lib_sysinfo.pcie_ctrl_base + PCIE_CFG_OFFSET_ADDR;
}