Fix register typo for core 2 cpus (trivial)
This bug was reported a long time ago by Thomas Jourdan. Thanks a lot Thomas. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -39,7 +39,7 @@ cache_as_ram:
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movl %eax, (%esi)
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movl %eax, (%esi)
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/* Disable prefetchers */
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/* Disable prefetchers */
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movl $0x01a0, %eax
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movl $0x01a0, %ecx
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rdmsr
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rdmsr
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orl $((1 << 9) | (1 << 19)), %eax
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orl $((1 << 9) | (1 << 19)), %eax
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orl $((1 << 5) | (1 << 7)), %edx
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orl $((1 << 5) | (1 << 7)), %edx
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