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Fix register typo for core 2 cpus (trivial) 

This bug was reported a long time ago by Thomas Jourdan. Thanks a lot Thomas.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2009-01-20 21:32:37 +00:00 committed by Stefan Reinauer
parent c5983305ef
commit 20b261dacf
1 changed files with 1 additions and 1 deletions
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2
src/cpu/intel/model_6fx/cache_as_ram.inc
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@ -39,7 +39,7 @@ cache_as_ram:
movl %eax, (%esi)
/* Disable prefetchers */
movl $0x01a0, %eax
movl $0x01a0, %ecx
rdmsr
orl $((1 << 9) | (1 << 19)), %eax
orl $((1 << 5) | (1 << 7)), %edx