target config fixup
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1823 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
parent
970990800e
commit
20bd731b75
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@ -1,111 +1,20 @@
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# Sample config file for building AMD Quartet images
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# This will make a target directory of ./quartet
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loadoptions
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# AMD Quartet
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target quartet
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mainboard amd/quartet
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uses ARCH
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uses CONFIG_COMPRESS
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uses CONFIG_IOAPIC
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uses CONFIG_ROM_STREAM
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uses CONFIG_ROM_STREAM_START
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uses CONFIG_UDELAY_TSC
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uses CPU_FIXUP
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uses FALLBACK_SIZE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses HAVE_HARD_RESET
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uses i586
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uses i686
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uses INTEL_PPRO_MTRR
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uses HEAP_SIZE
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uses IRQ_SLOT_COUNT
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uses k7
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uses k8
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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uses CONFIG_SMP
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uses CONFIG_MAX_CPUS
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uses MEMORY_HOLE
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uses PAYLOAD_SIZE
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uses _RAMBASE
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uses _ROMBASE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_OFFSET
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uses ROM_SECTION_SIZE
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uses ROM_SIZE
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uses STACK_SIZE
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uses USE_FALLBACK_IMAGE
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uses USE_OPTION_TABLE
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uses HAVE_OPTION_TABLE
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses CONFIG_CONSOLE_SERIAL8250
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uses MAINBOARD
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uses CONFIG_CHIP_CONFIGURE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses LINUXBIOS_EXTRA_VERSION
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uses HAVE_ACPI_TABLES
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uses CC
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option CC="gcc -m32"
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option CONFIG_CHIP_CONFIGURE=1
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option MAXIMUM_CONSOLE_LOGLEVEL=7
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option DEFAULT_CONSOLE_LOGLEVEL=7
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option CONFIG_CONSOLE_SERIAL8250=1
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option CPU_FIXUP=1
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option CONFIG_UDELAY_TSC=0
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option i686=1
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option i586=1
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option INTEL_PPRO_MTRR=1
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option k7=1
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option k8=1
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option ROM_SIZE=524288
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option HAVE_OPTION_TABLE=1
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option CONFIG_ROM_STREAM=1
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option HAVE_FALLBACK_BOOT=1
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option HAVE_HARD_RESET=1
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option HAVE_ACPI_TABLES=1
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###
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### Compute the location and size of where this firmware image
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### (linuxBIOS plus bootloader) will live in the boot rom chip.
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###
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option FALLBACK_SIZE=0x40000
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## LinuxBIOS C code runs at this location in RAM
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option _RAMBASE=0x00004000
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#
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###
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### Compute the start location and size size of
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### The linuxBIOS bootloader.
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###
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#
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# AMD Quartet
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romimage "normal"
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option USE_FALLBACK_IMAGE=0
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option ROM_IMAGE_SIZE=0x10000
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option LINUXBIOS_EXTRA_VERSION=".0Normal"
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mainboard amd/quartet
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payload /suse/stepan/tg3--ide_disk.zelf
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option LINUXBIOS_EXTRA_VERSION=".0-Normal"
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payload /usr/share/LinuxBIOS/tg3--ide_disk.zelf
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end
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romimage "fallback"
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option USE_FALLBACK_IMAGE=1
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option ROM_IMAGE_SIZE=0x10000
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option LINUXBIOS_EXTRA_VERSION=".0Fallback"
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mainboard amd/quartet
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payload /suse/stepan/tg3--ide_disk.zelf
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option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
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payload /usr/share/LinuxBIOS/tg3--ide_disk.zelf
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end
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buildrom ./quartet.rom ROM_SIZE "normal" "fallback"
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@ -1,113 +1,20 @@
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# the AMD Serenade
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# This will make a target directory of ./e325
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loadoptions
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# AMD Serenade
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target serenade
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mainboard amd/serenade
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uses ARCH
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uses CONFIG_COMPRESS
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uses CONFIG_IOAPIC
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uses CONFIG_ROM_STREAM
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uses CONFIG_ROM_STREAM_START
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uses CONFIG_SERIAL_POST
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uses NO_POST
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uses CONFIG_UDELAY_TSC
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uses CPU_FIXUP
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uses FALLBACK_SIZE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses HAVE_HARD_RESET
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uses i586
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uses i686
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uses INTEL_PPRO_MTRR
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uses HEAP_SIZE
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uses IRQ_SLOT_COUNT
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uses k7
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uses k8
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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uses CONFIG_SMP
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uses CONFIG_MAX_CPUS
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uses MEMORY_HOLE
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uses PAYLOAD_SIZE
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uses _RAMBASE
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uses _ROMBASE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_OFFSET
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uses ROM_SECTION_SIZE
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uses ROM_SIZE
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uses STACK_SIZE
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uses USE_FALLBACK_IMAGE
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uses USE_OPTION_TABLE
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uses HAVE_OPTION_TABLE
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses CONFIG_CONSOLE_SERIAL8250
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uses MAINBOARD
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uses CONFIG_CHIP_CONFIGURE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses LINUXBIOS_EXTRA_VERSION
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option CONFIG_CHIP_CONFIGURE=1
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option MAXIMUM_CONSOLE_LOGLEVEL=8
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option DEFAULT_CONSOLE_LOGLEVEL=8
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option CONFIG_CONSOLE_SERIAL8250=1
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option CONFIG_SERIAL_POST=1
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option NO_POST=0
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option CPU_FIXUP=1
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option CONFIG_UDELAY_TSC=0
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option i686=1
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option i586=1
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option INTEL_PPRO_MTRR=1
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option k7=1
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option k8=1
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option ROM_SIZE=1048576
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option HAVE_OPTION_TABLE=1
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option CONFIG_ROM_STREAM=1
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option HAVE_FALLBACK_BOOT=1
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###
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### Compute the location and size of where this firmware image
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### (linuxBIOS plus bootloader) will live in the boot rom chip.
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###
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option FALLBACK_SIZE=131072
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## LinuxBIOS C code runs at this location in RAM
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option _RAMBASE=0x00004000
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#
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###
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### Compute the start location and size size of
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### The linuxBIOS bootloader.
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###
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#
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# Arima hdama
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romimage "normal"
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option USE_FALLBACK_IMAGE=0
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option ROM_IMAGE_SIZE=0x10000
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option LINUXBIOS_EXTRA_VERSION=".0Normal"
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mainboard amd/serenade
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option LINUXBIOS_EXTRA_VERSION=".0-Normal"
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payload /home/ollie/work/filo-0.4.1/filo.elf
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end
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romimage "fallback"
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option USE_FALLBACK_IMAGE=1
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option ROM_IMAGE_SIZE=0x10000
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option LINUXBIOS_EXTRA_VERSION=".0Fallback"
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mainboard amd/serenade
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option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
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payload /home/ollie/work/filo-0.4.1/filo.elf
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# use this to test a build if you don't have the etherboot
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# payload /etc/hosts
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end
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buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
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buildrom ./serenade.rom ROM_SIZE "normal" "fallback"
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@ -1,102 +1,24 @@
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# This config file will build an image without normal/fallback mechanism
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# but with a kernel image builtin instead
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#
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# This has not been tested due to a bug in the SST49LF080A
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# AMD Solo
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# This will make a target directory of ./solo
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loadoptions
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target solo-8mbit
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uses ARCH
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uses CONFIG_COMPRESS
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uses CONFIG_IOAPIC
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uses CONFIG_ROM_STREAM
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uses CONFIG_ROM_STREAM_START
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uses CONFIG_UDELAY_TSC
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uses CPU_FIXUP
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uses FALLBACK_SIZE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses HAVE_HARD_RESET
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uses i586
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uses i686
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uses INTEL_PPRO_MTRR
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uses HEAP_SIZE
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uses IRQ_SLOT_COUNT
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uses k7
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uses k8
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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uses CONFIG_SMP
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uses CONFIG_MAX_CPUS
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uses MEMORY_HOLE
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uses PAYLOAD_SIZE
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uses _RAMBASE
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uses _ROMBASE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_OFFSET
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uses ROM_SECTION_SIZE
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uses ROM_SIZE
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uses STACK_SIZE
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uses USE_FALLBACK_IMAGE
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uses USE_OPTION_TABLE
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uses HAVE_OPTION_TABLE
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses CONFIG_CONSOLE_SERIAL8250
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uses MAINBOARD
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uses CONFIG_CHIP_CONFIGURE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses LINUXBIOS_EXTRA_VERSION
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uses CC
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option CC="gcc -m32"
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option CONFIG_CHIP_CONFIGURE=1
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option MAXIMUM_CONSOLE_LOGLEVEL=8
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option DEFAULT_CONSOLE_LOGLEVEL=8
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option CONFIG_CONSOLE_SERIAL8250=1
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option CPU_FIXUP=1
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option CONFIG_UDELAY_TSC=0
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option i686=1
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option i586=1
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option INTEL_PPRO_MTRR=1
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option k7=1
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option k8=1
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mainboard amd/solo
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option ROM_SIZE=0x100000
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option HAVE_OPTION_TABLE=1
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option CONFIG_ROM_STREAM=1
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option HAVE_FALLBACK_BOOT=1
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###
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### Compute the location and size of where this firmware image
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### (linuxBIOS plus bootloader) will live in the boot rom chip.
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###
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option FALLBACK_SIZE=ROM_SIZE
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## LinuxBIOS C code runs at this location in RAM
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option _RAMBASE=0x00004000
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#
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###
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### Compute the start location and size size of
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### The linuxBIOS bootloader.
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###
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romimage "single"
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option USE_FALLBACK_IMAGE=1
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romimage "normal"
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option USE_FALLBACK_IMAGE=0
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option ROM_IMAGE_SIZE=0x10000
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option LINUXBIOS_EXTRA_VERSION=".0-8MBit"
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mainboard amd/solo
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option LINUXBIOS_EXTRA_VERSION=".0-Normal"
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payload /usr/share/LinuxBIOS/kernelpayload.elf
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end
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buildrom ./linuxbios.rom ROM_SIZE "single"
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romimage "fallback"
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option USE_FALLBACK_IMAGE=1
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option ROM_IMAGE_SIZE=0x10000
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option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
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payload /usr/share/LinuxBIOS/kernelpayload.elf
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end
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buildrom ./solo-8mbit.rom ROM_SIZE "normal" "fallback"
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