GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/skylake: Set PsysPL2 MSR 

BUG=b:7473486, b:35775024
BRANCH=None
TEST=On bootup make sure PL2 and PsysPL2 values set
     properly (through debug output)

Change-Id: I847a8458382e7db1689b426f32ff2dcbc5a0899c
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Shelley Chen 2017-06-29 11:31:16 -07:00 committed by Aaron Durbin
parent 2a7fbea3f1
commit 20c3ea5c4f
3 changed files with 20 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/intel/skylake/chip.h
View File

@ -97,6 +97,9 @@ struct soc_intel_skylake_config {
/* PL2 Override value in Watts */ /* PL2 Override value in Watts */
u32 tdp_pl2_override; u32 tdp_pl2_override;
/* SysPL2 Value in Watts */
u32 tdp_psyspl2;
/* /*
* The following fields come from FspUpdVpd.h. * The following fields come from FspUpdVpd.h.
* These are configuration values that are passed to FSP during * These are configuration values that are passed to FSP during

17
src/soc/intel/skylake/cpu.c
View File

@ -160,10 +160,11 @@ void set_power_limits(u8 power_limit_1_time)
limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
PKG_POWER_LIMIT_TIME_SHIFT; PKG_POWER_LIMIT_TIME_SHIFT;
/* Set short term power limit to 1.25 * TDP */ /* Set short term power limit to 1.25 * TDP if no config given */
limit.hi = 0; limit.hi = 0;
tdp_pl2 = (conf->tdp_pl2_override == 0) ? tdp_pl2 = (conf->tdp_pl2_override == 0) ?
(tdp * 125) / 100 : (conf->tdp_pl2_override * power_unit); (tdp * 125) / 100 : (conf->tdp_pl2_override * power_unit);
printk(BIOS_DEBUG, "CPU PL2 = %u Watts\n", tdp_pl2 / power_unit);
limit.hi |= (tdp_pl2) & PKG_POWER_LIMIT_MASK; limit.hi |= (tdp_pl2) & PKG_POWER_LIMIT_MASK;
limit.hi |= PKG_POWER_LIMIT_CLAMP; limit.hi |= PKG_POWER_LIMIT_CLAMP;
limit.hi |= PKG_POWER_LIMIT_EN; limit.hi |= PKG_POWER_LIMIT_EN;
@ -175,6 +176,20 @@ void set_power_limits(u8 power_limit_1_time)
MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo & (~(PKG_POWER_LIMIT_EN)); MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo & (~(PKG_POWER_LIMIT_EN));
MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi;
/* Set PsysPl2 */
if (conf->tdp_psyspl2) {
limit = rdmsr(MSR_PLATFORM_POWER_LIMIT);
limit.hi = 0;
printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n",
conf->tdp_psyspl2);
limit.hi |= (conf->tdp_psyspl2 * power_unit) &
PKG_POWER_LIMIT_MASK;
limit.hi |= PKG_POWER_LIMIT_CLAMP;
limit.hi |= PKG_POWER_LIMIT_EN;
wrmsr(MSR_PLATFORM_POWER_LIMIT, limit);
}
/* Set DDR RAPL power limit by copying from MMIO to MSR */ /* Set DDR RAPL power limit by copying from MMIO to MSR */
msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO);
msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI);

1
src/soc/intel/skylake/include/soc/msr.h
View File

@ -37,5 +37,6 @@
#define MSR_VR_MISC_CONFIG2 0x636 #define MSR_VR_MISC_CONFIG2 0x636
#define MSR_PP0_POWER_LIMIT 0x638 #define MSR_PP0_POWER_LIMIT 0x638
#define MSR_PP1_POWER_LIMIT 0x640 #define MSR_PP1_POWER_LIMIT 0x640
#define MSR_PLATFORM_POWER_LIMIT 0x65c
#endif #endif