From 20c8aa71d140d682f343892b2526001e7f528d49 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 11 Dec 2020 17:44:08 +0100 Subject: [PATCH] soc/intel/braswell: Use Kconfig value for TSEG size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SoC selects HAVE_SMI_HANDLER, so TsegSize is always set to 8 MiB. Also, use SMM_TSEG_SIZE in place of a magic number. Change-Id: I139e1073426051fea5d30b6ce3dd9746e0e985a2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/48578 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Frans Hendriks Reviewed-by: Furquan Shaikh --- src/soc/intel/braswell/romstage/romstage.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 37ee93cd24..1738679b1e 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -113,7 +114,7 @@ void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd config = config_of(dev); printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); - upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ? 8 : 0; + upd->PcdMrcInitTsegSize = CONFIG_SMM_TSEG_SIZE / MiB; upd->PcdMrcInitMmioSize = 0x800; upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1; upd->PcdMrcInitSpdAddr2 = config->PcdMrcInitSpdAddr2;