adding support for dell 1850
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
3182cad1a3
commit
20d943d9f9
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@ -48,91 +48,6 @@
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#define OUTC(addr, val) *(unsigned char *)(addr) = (val)
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void p4(unsigned char c){
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//print_err("TRY A TX NIBLE\r\n");
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__console_tx_nibble(c);
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return;
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print_err("now do the other\r\n");
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// c = c + '0';
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// if (c > '9')
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// c = c + 39;
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// __console_tx_byte(c);
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//print_err("NO!\r\n");
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// return;
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switch(c) {
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case 0:
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print_err("0");
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break;
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case 1:
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print_err("1");
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break;
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case 2:
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print_err("2");
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break;
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case 3:
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print_err("3");
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break;
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case 4:
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print_err("4");
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break;
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case 5:
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print_err("5");
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break;
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case 6:
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print_err("6");
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break;
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case 7:
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print_err("7");
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break;
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case 8:
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print_err("8");
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break;
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case 9:
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print_err("9");
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break;
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case 0xa:
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print_err("a");
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break;
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case 0xb:
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print_err("b");
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break;
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case 0xc:
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print_err("c");
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break;
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case 0xd:
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print_err("d");
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break;
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case 0xe:
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print_err("e");
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break;
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case 0xf:
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print_err("f");
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break;
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}
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}
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void p8(unsigned char c) {
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/*
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__console_tx_nibble(c>>4);
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__console_tx_nibble(c&0xf);
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*/
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p4(c>>4);
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p4(c&0xf);
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}
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void p16(unsigned short s) {
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p8(s>>16);
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p8(s);
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}
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void p32(unsigned long l) {
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p16(l>>16);
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p16(l);
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}
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/* sadly, romcc can't quite handle what we want, so we do this ugly thing */
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#define drcctl (( volatile unsigned char *)0xfffef010)
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#define drcmctl (( volatile unsigned char *)0xfffef012)
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@ -384,17 +299,25 @@ int sizemem(void)
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volatile unsigned long *lp = (volatile unsigned long *) CACHELINESZ;
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unsigned long l;
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/* initialize dram controller registers */
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*dbctl = 0; /* disable write buffer/read-ahead buffer */
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/* disable write buffer/read-ahead buffer */
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*dbctl = 0;
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/* no ecc interrupts of any kind. */
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*eccctl = 0;
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*drcmctl = 0x1e; /* Set SDRAM timing for slowest speed. */
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/* Set SDRAM timing for slowest speed. */
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*drcmctl = 0x1e;
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/* setup dram register for all banks
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* with max cols and max banks
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* this is the oldest trick in the book. You are going to set up for max rows
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* and cols, then do a write, then see if the data is wrapped to low memory.
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* you can actually tell by which data gets to which low memory,
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* exactly how many rows and cols you have.
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*/
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*drccfg=0xbbbb;
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/* setup loop to do 4 external banks starting with bank 3 */
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*drcbendadr=0x0ff000000;
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/* for now, set it up for one loop of bank 0. Just to get it to go at all. */
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*drcbendadr=0x0ff;
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/* issue a NOP to all DRAMs */
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@ -407,7 +330,7 @@ int sizemem(void)
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dummy_write();
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print_err("NOP\n");
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/* 100? 200? */
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//sc520_udelay(100);
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udelay(100);
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print_err("after sc520_udelay\r\n");
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/* issue all banks precharge */
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@ -743,7 +666,6 @@ staticmem(void){
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print_err("NO LUCK\r\n");
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else
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print_err("did a stor and load ...\r\n");
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// p32(*zero);
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print_err_hex32(*zero);
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// print_err(" zero is now "); print_err_hex32(*zero); print_err("\r\n");
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}
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@ -0,0 +1,209 @@
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##
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## Only use the option table in a normal image
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##
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default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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else
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_OFFSET = 0
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end
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##
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up linuxBIOS,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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default XIP_ROM_SIZE=131072
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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object reset.o
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##
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## Romcc output
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##
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c ./romcc"
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action "./romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(MAINBOARD)/failover.c ./romcc"
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action "./romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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action "./romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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action "./romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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###
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit cpu/x86/mmx/enable_mmx.inc
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mainboardinit cpu/x86/sse/enable_sse.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/x86/sse/disable_sse.inc
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mainboardinit cpu/x86/mmx/disable_mmx.inc
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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chip northbridge/intel/E7520 # mch
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device pci_domain 0 on
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chip southbridge/intel/ich5r # ich5r
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# USB ports
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device pci 1d.0 on end
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device pci 1d.1 on end
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device pci 1d.2 on end
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device pci 1d.3 on end
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device pci 1d.7 on end
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# -> Bridge
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device pci 1e.0 on end
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# -> ISA
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device pci 1f.0 on
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chip superio/winbond/w83627hf
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device pnp 2e.0 off end
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device pnp 2e.2 on
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.4 off end
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device pnp 2e.5 off end
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device pnp 2e.6 off end
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device pnp 2e.7 off end
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device pnp 2e.9 off end
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device pnp 2e.a on end
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device pnp 2e.b off end
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end
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end
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# -> IDE
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device pci 1f.1 on end
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# -> SATA
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device pci 1f.2 on end
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device pci 1f.3 on end
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register "pirq_a_d" = "0x0b070a05"
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register "pirq_e_h" = "0x0a808080"
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end
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device pci 00.0 on end
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device pci 00.1 on end
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device pci 01.0 on end
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device pci 02.0 on
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chip southbridge/intel/pxhd # pxhd1
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# Bus bridges and ioapics usually bus 1
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device pci 0.0 on
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# On board gig e1000
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chip drivers/generic/generic
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device pci 03.0 on end
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device pci 03.1 on end
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end
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end
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device pci 0.1 on end
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device pci 0.2 on end
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device pci 0.3 on end
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end
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end
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device pci 04.0 on end
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device pci 06.0 on end
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end
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device apic_cluster 0 on
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chip cpu/intel/socket_mPGA604_800Mhz # cpu 0
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device apic 0 on end
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end
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chip cpu/intel/socket_mPGA604_800Mhz # cpu 1
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device apic 6 on end
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end
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end
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register "intrline" = "0x00070105"
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end
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@ -0,0 +1,228 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses IRQ_SLOT_COUNT
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uses HAVE_OPTION_TABLE
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uses CONFIG_LOGICAL_CPUS
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uses CONFIG_MAX_CPUS
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uses CONFIG_IOAPIC
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uses CONFIG_SMP
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uses FALLBACK_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_STREAM
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uses CONFIG_ROM_STREAM_START
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses USE_OPTION_TABLE
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uses LB_CKS_RANGE_START
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uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses MAINBOARD
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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uses LINUXBIOS_EXTRA_VERSION
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uses CONFIG_UDELAY_TSC
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uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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uses _RAMBASE
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uses CONFIG_GDB_STUB
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uses CONFIG_CONSOLE_SERIAL8250
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uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
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uses CONFIG_CONSOLE_BTEXT
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uses CC
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uses HOSTCC
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uses CROSS_COMPILE
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uses OBJCOPY
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###
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### Build options
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###
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##
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## ROM_SIZE is the size of boot ROM that this board will use.
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##
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default ROM_SIZE=1048576
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##
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## Build code for the fallback boot
|
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##
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default HAVE_FALLBACK_BOOT=1
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##
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## Delay timer options
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## Use timer2
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##
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default CONFIG_UDELAY_TSC=1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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default HAVE_HARD_RESET=1
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=16
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##
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## Build code to export an x86 MP table
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## Useful for specifying IRQ routing values
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##
|
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default HAVE_MP_TABLE=1
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##
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## Build code to export a CMOS option table
|
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##
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default HAVE_OPTION_TABLE=1
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##
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## Move the default LinuxBIOS cmos range off of AMD RTC registers
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##
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default LB_CKS_RANGE_START=49
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default LB_CKS_RANGE_END=122
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default LB_CKS_LOC=123
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##
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## Build code for SMP support
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## Only worry about 2 micro processors
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##
|
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default CONFIG_SMP=1
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default CONFIG_MAX_CPUS=4
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default CONFIG_LOGICAL_CPUS=0
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##
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## Build code to setup a generic IOAPIC
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##
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default CONFIG_IOAPIC=1
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##
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## Clean up the motherboard id strings
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##
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default MAINBOARD_PART_NUMBER="X6DHR"
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default MAINBOARD_VENDOR= "Supermicro"
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default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
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default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
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###
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### LinuxBIOS layout values
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###
|
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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default ROM_IMAGE_SIZE = 65536
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##
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## Use a small 8K stack
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##
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default STACK_SIZE=0x2000
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##
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## Use a small 32K heap
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##
|
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default HEAP_SIZE=0x8000
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|
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|
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###
|
||||
### Compute the location and size of where this firmware image
|
||||
### (linuxBIOS plus bootloader) will live in the boot rom chip.
|
||||
###
|
||||
default FALLBACK_SIZE=131072
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##
|
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## LinuxBIOS C code runs at this location in RAM
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||||
##
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default _RAMBASE=0x00004000
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##
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## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_STREAM=1
|
||||
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||||
|
||||
###
|
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### Defaults of options that you may want to override in the target config file
|
||||
###
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##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="$(CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## Disable the gdb stub by default
|
||||
##
|
||||
default CONFIG_GDB_STUB=0
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default TTYS0_BAUD=115200
|
||||
#default TTYS0_BAUD=57600
|
||||
#default TTYS0_BAUD=38400
|
||||
#default TTYS0_BAUD=19200
|
||||
#default TTYS0_BAUD=9600
|
||||
#default TTYS0_BAUD=4800
|
||||
#default TTYS0_BAUD=2400
|
||||
#default TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the linuxBIOS loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
##
|
||||
## Don't enable the btext console
|
||||
##
|
||||
default CONFIG_CONSOLE_BTEXT=0
|
||||
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -0,0 +1,169 @@
|
|||
#define ASSEMBLY 1
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include "option_table.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
#include "pc80/serial.c"
|
||||
#include "arch/i386/lib/console.c"
|
||||
#include "ram/ramtest.c"
|
||||
#include "southbridge/intel/ich5r/ich5r_early_smbus.c"
|
||||
#include "northbridge/intel/E7520/raminit.h"
|
||||
#include "superio/winbond/w83627hf/w83627hf.h"
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "cpu/x86/mtrr/earlymtrr.c"
|
||||
#include "debug.c"
|
||||
#include "watchdog.c"
|
||||
#include "reset.c"
|
||||
#include "s2850_fixups.c"
|
||||
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
|
||||
#include "northbridge/intel/E7520/memory_initialized.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
|
||||
|
||||
#define SIO_GPIO_BASE 0x680
|
||||
#define SIO_XBUS_BASE 0x4880
|
||||
|
||||
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2)
|
||||
|
||||
#define DEVPRES_CONFIG ( \
|
||||
DEVPRES_D0F0 | \
|
||||
DEVPRES_D1F0 | \
|
||||
DEVPRES_D2F0 | \
|
||||
DEVPRES_D3F0 | \
|
||||
DEVPRES_D4F0 | \
|
||||
DEVPRES_D6F0 | \
|
||||
0 )
|
||||
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
|
||||
|
||||
#define RECVENA_CONFIG 0x0808090a
|
||||
#define RECVENB_CONFIG 0x0808090a
|
||||
|
||||
//void udelay(int usecs)
|
||||
//{
|
||||
// int i;
|
||||
// for(i = 0; i < usecs; i++)
|
||||
// outb(i&0xff, 0x80);
|
||||
//}
|
||||
|
||||
#if 0
|
||||
static void hard_reset(void)
|
||||
{
|
||||
/* enable cf9 */
|
||||
pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
|
||||
/* reset */
|
||||
outb(0x0e, 0x0cf9);
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline void activate_spd_rom(const struct mem_controller *ctrl)
|
||||
{
|
||||
/* nothing to do */
|
||||
}
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/intel/E7520/raminit.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
||||
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
/*
|
||||
*
|
||||
*
|
||||
*/
|
||||
static const struct mem_controller mch[] = {
|
||||
{
|
||||
.node_id = 0,
|
||||
.f0 = PCI_DEV(0, 0x00, 0),
|
||||
.f1 = PCI_DEV(0, 0x00, 1),
|
||||
.f2 = PCI_DEV(0, 0x00, 2),
|
||||
.f3 = PCI_DEV(0, 0x00, 3),
|
||||
.channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
|
||||
.channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
|
||||
}
|
||||
};
|
||||
|
||||
if (bist == 0) {
|
||||
/* Skip this if there was a built in self test failure */
|
||||
early_mtrr_init();
|
||||
if (memory_initialized()) {
|
||||
asm volatile ("jmp __cpu_reset");
|
||||
}
|
||||
}
|
||||
/* Setup the console */
|
||||
outb(0x87,0x2e);
|
||||
outb(0x87,0x2e);
|
||||
pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
|
||||
w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
// report_bist_failure(bist);
|
||||
|
||||
/* MOVE ME TO A BETTER LOCATION !!! */
|
||||
/* config LPC decode for flash memory access */
|
||||
device_t dev;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
|
||||
if (dev == PCI_DEV_INVALID) {
|
||||
die("Missing ich5?");
|
||||
}
|
||||
pci_write_config32(dev, 0xe8, 0x00000000);
|
||||
pci_write_config8(dev, 0xf0, 0x00);
|
||||
|
||||
#if 0
|
||||
display_cpuid_update_microcode();
|
||||
#endif
|
||||
#if 0
|
||||
print_pci_devices();
|
||||
#endif
|
||||
#if 1
|
||||
enable_smbus();
|
||||
#endif
|
||||
#if 0
|
||||
// dump_spd_registers(&cpu[0]);
|
||||
int i;
|
||||
for(i = 0; i < 1; i++) {
|
||||
dump_spd_registers();
|
||||
}
|
||||
#endif
|
||||
disable_watchdogs();
|
||||
// dump_ipmi_registers();
|
||||
mainboard_set_e7520_leds();
|
||||
// memreset_setup();
|
||||
sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
|
||||
#if 0
|
||||
dump_pci_devices();
|
||||
#endif
|
||||
#if 0
|
||||
dump_pci_device(PCI_DEV(0, 0x00, 0));
|
||||
dump_bar14(PCI_DEV(0, 0x00, 0));
|
||||
#endif
|
||||
|
||||
#if 0 // temporarily disabled
|
||||
/* Check the first 1M */
|
||||
// ram_check(0x00000000, 0x000100000);
|
||||
// ram_check(0x00000000, 0x000a0000);
|
||||
// ram_check(0x00100000, 0x01000000);
|
||||
ram_check(0x00100000, 0x00100100);
|
||||
/* check the first 1M in the 3rd Gig */
|
||||
// ram_check(0x30100000, 0x31000000);
|
||||
#endif
|
||||
#if 0
|
||||
ram_check(0x00000000, 0x02000000);
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
while(1) {
|
||||
hlt();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
struct chip_operations mainboard_dell_s2850_ops;
|
||||
|
||||
struct mainboard_dell_s2850_config {
|
||||
int nothing;
|
||||
};
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
395 1 e 2 hyper_threading
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 reserved_memory
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,330 @@
|
|||
#define SMBUS_MEM_DEVICE_START 0x50
|
||||
#define SMBUS_MEM_DEVICE_END 0x57
|
||||
#define SMBUS_MEM_DEVICE_INC 1
|
||||
|
||||
static void print_reg(unsigned char index)
|
||||
{
|
||||
unsigned char data;
|
||||
|
||||
outb(index, 0x2e);
|
||||
data = inb(0x2f);
|
||||
print_debug("0x");
|
||||
print_debug_hex8(index);
|
||||
print_debug(": 0x");
|
||||
print_debug_hex8(data);
|
||||
print_debug("\r\n");
|
||||
return;
|
||||
}
|
||||
|
||||
static void xbus_en(void)
|
||||
{
|
||||
/* select the XBUS function in the SIO */
|
||||
outb(0x07, 0x2e);
|
||||
outb(0x0f, 0x2f);
|
||||
outb(0x30, 0x2e);
|
||||
outb(0x01, 0x2f);
|
||||
return;
|
||||
}
|
||||
|
||||
static void setup_func(unsigned char func)
|
||||
{
|
||||
/* select the function in the SIO */
|
||||
outb(0x07, 0x2e);
|
||||
outb(func, 0x2f);
|
||||
/* print out the regs */
|
||||
print_reg(0x30);
|
||||
print_reg(0x60);
|
||||
print_reg(0x61);
|
||||
print_reg(0x62);
|
||||
print_reg(0x63);
|
||||
print_reg(0x70);
|
||||
print_reg(0x71);
|
||||
print_reg(0x74);
|
||||
print_reg(0x75);
|
||||
return;
|
||||
}
|
||||
|
||||
static void siodump(void)
|
||||
{
|
||||
int i;
|
||||
unsigned char data;
|
||||
|
||||
print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
|
||||
for (i=0x10; i<=0x2d; i++) {
|
||||
print_reg((unsigned char)i);
|
||||
}
|
||||
#if 0
|
||||
print_debug("\r\n*** XBUS REGISTERS ***\r\n");
|
||||
setup_func(0x0f);
|
||||
for (i=0xf0; i<=0xff; i++) {
|
||||
print_reg((unsigned char)i);
|
||||
}
|
||||
|
||||
print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n");
|
||||
setup_func(0x03);
|
||||
print_reg(0xf0);
|
||||
|
||||
print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n");
|
||||
setup_func(0x02);
|
||||
print_reg(0xf0);
|
||||
|
||||
#endif
|
||||
print_debug("\r\n*** GPIO REGISTERS ***\r\n");
|
||||
setup_func(0x07);
|
||||
for (i=0xf0; i<=0xf8; i++) {
|
||||
print_reg((unsigned char)i);
|
||||
}
|
||||
print_debug("\r\n*** GPIO VALUES ***\r\n");
|
||||
data = inb(0x68a);
|
||||
print_debug("\r\nGPDO 4: 0x");
|
||||
print_debug_hex8(data);
|
||||
data = inb(0x68b);
|
||||
print_debug("\r\nGPDI 4: 0x");
|
||||
print_debug_hex8(data);
|
||||
print_debug("\r\n");
|
||||
|
||||
#if 0
|
||||
|
||||
print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n");
|
||||
setup_func(0x0a);
|
||||
print_reg(0xf0);
|
||||
|
||||
print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n");
|
||||
setup_func(0x09);
|
||||
print_reg(0xf0);
|
||||
print_reg(0xf1);
|
||||
|
||||
print_debug("\r\n*** RTC REGISTERS ***\r\n");
|
||||
setup_func(0x10);
|
||||
print_reg(0xf0);
|
||||
print_reg(0xf1);
|
||||
print_reg(0xf3);
|
||||
print_reg(0xf6);
|
||||
print_reg(0xf7);
|
||||
print_reg(0xfe);
|
||||
print_reg(0xff);
|
||||
|
||||
print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
|
||||
setup_func(0x14);
|
||||
print_reg(0xf0);
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
static void print_debug_pci_dev(unsigned dev)
|
||||
{
|
||||
print_debug("PCI: ");
|
||||
print_debug_hex8((dev >> 16) & 0xff);
|
||||
print_debug_char(':');
|
||||
print_debug_hex8((dev >> 11) & 0x1f);
|
||||
print_debug_char('.');
|
||||
print_debug_hex8((dev >> 8) & 7);
|
||||
}
|
||||
|
||||
static void print_pci_devices(void)
|
||||
{
|
||||
device_t dev;
|
||||
for(dev = PCI_DEV(0, 0, 0);
|
||||
dev <= PCI_DEV(0, 0x1f, 0x7);
|
||||
dev += PCI_DEV(0,0,1)) {
|
||||
uint32_t id;
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0x0000)) {
|
||||
continue;
|
||||
}
|
||||
print_debug_pci_dev(dev);
|
||||
print_debug("\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void dump_pci_device(unsigned dev)
|
||||
{
|
||||
int i;
|
||||
print_debug_pci_dev(dev);
|
||||
print_debug("\r\n");
|
||||
|
||||
for(i = 0; i <= 255; i++) {
|
||||
unsigned char val;
|
||||
if ((i & 0x0f) == 0) {
|
||||
print_debug_hex8(i);
|
||||
print_debug_char(':');
|
||||
}
|
||||
val = pci_read_config8(dev, i);
|
||||
print_debug_char(' ');
|
||||
print_debug_hex8(val);
|
||||
if ((i & 0x0f) == 0x0f) {
|
||||
print_debug("\r\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void dump_bar14(unsigned dev)
|
||||
{
|
||||
int i;
|
||||
unsigned long bar;
|
||||
|
||||
print_debug("BAR 14 Dump\r\n");
|
||||
|
||||
bar = pci_read_config32(dev, 0x14);
|
||||
for(i = 0; i <= 0x300; i+=4) {
|
||||
#if 0
|
||||
unsigned char val;
|
||||
if ((i & 0x0f) == 0) {
|
||||
print_debug_hex8(i);
|
||||
print_debug_char(':');
|
||||
}
|
||||
val = pci_read_config8(dev, i);
|
||||
#endif
|
||||
if((i%4)==0) {
|
||||
print_debug("\r\n");
|
||||
print_debug_hex16(i);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug_hex32(read32(bar + i));
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\r\n");
|
||||
}
|
||||
|
||||
static void dump_pci_devices(void)
|
||||
{
|
||||
device_t dev;
|
||||
for(dev = PCI_DEV(0, 0, 0);
|
||||
dev <= PCI_DEV(0, 0x1f, 0x7);
|
||||
dev += PCI_DEV(0,0,1)) {
|
||||
uint32_t id;
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0x0000)) {
|
||||
continue;
|
||||
}
|
||||
dump_pci_device(dev);
|
||||
}
|
||||
}
|
||||
|
||||
#if 0
|
||||
static void dump_spd_registers(const struct mem_controller *ctrl)
|
||||
{
|
||||
int i;
|
||||
print_debug("\r\n");
|
||||
for(i = 0; i < 4; i++) {
|
||||
unsigned device;
|
||||
device = ctrl->channel0[i];
|
||||
if (device) {
|
||||
int j;
|
||||
print_debug("dimm: ");
|
||||
print_debug_hex8(i);
|
||||
print_debug(".0: ");
|
||||
print_debug_hex8(device);
|
||||
for(j = 0; j < 256; j++) {
|
||||
int status;
|
||||
unsigned char byte;
|
||||
if ((j & 0xf) == 0) {
|
||||
print_debug("\r\n");
|
||||
print_debug_hex8(j);
|
||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, j);
|
||||
if (status < 0) {
|
||||
print_debug("bad device\r\n");
|
||||
break;
|
||||
}
|
||||
byte = status & 0xff;
|
||||
print_debug_hex8(byte);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\r\n");
|
||||
}
|
||||
device = ctrl->channel1[i];
|
||||
if (device) {
|
||||
int j;
|
||||
print_debug("dimm: ");
|
||||
print_debug_hex8(i);
|
||||
print_debug(".1: ");
|
||||
print_debug_hex8(device);
|
||||
for(j = 0; j < 256; j++) {
|
||||
int status;
|
||||
unsigned char byte;
|
||||
if ((j & 0xf) == 0) {
|
||||
print_debug("\r\n");
|
||||
print_debug_hex8(j);
|
||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, j);
|
||||
if (status < 0) {
|
||||
print_debug("bad device\r\n");
|
||||
break;
|
||||
}
|
||||
byte = status & 0xff;
|
||||
print_debug_hex8(byte);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\r\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
void dump_spd_registers(void)
|
||||
{
|
||||
unsigned device;
|
||||
device = SMBUS_MEM_DEVICE_START;
|
||||
while(device <= SMBUS_MEM_DEVICE_END) {
|
||||
int status = 0;
|
||||
int i;
|
||||
print_debug("\r\n");
|
||||
print_debug("dimm ");
|
||||
print_debug_hex8(device);
|
||||
|
||||
for(i = 0; (i < 256) ; i++) {
|
||||
unsigned char byte;
|
||||
if ((i % 16) == 0) {
|
||||
print_debug("\r\n");
|
||||
print_debug_hex8(i);
|
||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, i);
|
||||
if (status < 0) {
|
||||
print_debug("bad device: ");
|
||||
print_debug_hex8(-status);
|
||||
print_debug("\r\n");
|
||||
break;
|
||||
}
|
||||
print_debug_hex8(status);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
device += SMBUS_MEM_DEVICE_INC;
|
||||
print_debug("\n");
|
||||
}
|
||||
}
|
||||
|
||||
void dump_ipmi_registers(void)
|
||||
{
|
||||
unsigned device;
|
||||
device = 0x42;
|
||||
while(device <= 0x42) {
|
||||
int status = 0;
|
||||
int i;
|
||||
print_debug("\r\n");
|
||||
print_debug("ipmi ");
|
||||
print_debug_hex8(device);
|
||||
|
||||
for(i = 0; (i < 8) ; i++) {
|
||||
unsigned char byte;
|
||||
status = smbus_read_byte(device, 2);
|
||||
if (status < 0) {
|
||||
print_debug("bad device: ");
|
||||
print_debug_hex8(-status);
|
||||
print_debug("\r\n");
|
||||
break;
|
||||
}
|
||||
print_debug_hex8(status);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
device += SMBUS_MEM_DEVICE_INC;
|
||||
print_debug("\n");
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
#define ASSEMBLY 1
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include "pc80/serial.c"
|
||||
#include "arch/i386/lib/console.c"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "northbridge/intel/E7520/memory_initialized.c"
|
||||
|
||||
static unsigned long main(unsigned long bist)
|
||||
{
|
||||
/* Did just the cpu reset? */
|
||||
if (memory_initialized()) {
|
||||
if (last_boot_normal()) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto cpu_reset;
|
||||
}
|
||||
}
|
||||
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
normal_image:
|
||||
asm volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
cpu_reset:
|
||||
asm volatile ("jmp __cpu_reset"
|
||||
: /* outputs */
|
||||
: "a"(bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
fallback_image:
|
||||
return bist;
|
||||
}
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/* This file was generated by getpir.c, do not modify!
|
||||
(but if you do, please run checkpir on it to verify)
|
||||
* Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
|
||||
*
|
||||
* Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*17, /* there can be total 17 devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
|
||||
0, /* IRQs devoted exclusively to PCI usage */
|
||||
0x8086, /* Vendor */
|
||||
0x24d0, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0xc4, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00,(0x02<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
|
||||
{0x00,(0x04<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
|
||||
{0x00,(0x05<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
|
||||
{0x00,(0x06<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
|
||||
{0x05,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
|
||||
{0x01,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
|
||||
{0x00,(0x1d<<3)|0x0, {{0x60, 0xccf8}, {0x63, 0xccf8}, {0x62, 0xccf8}, {0x6b, 0x0ccf8}}, 0x0, 0x0},
|
||||
{0x09,(0x05<<3)|0x0, {{0x68, 0xccf8}, {0x69, 0xccf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
|
||||
{0x09,(0x06<<3)|0x0, {{0x6b, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
|
||||
{0x09,(0x0d<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
|
||||
{0x09,(0x03<<3)|0x0, {{0x63, 0xccf8}, {0x63, 0xccf8}, {0x63, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
|
||||
{0x06,(0x07<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
|
||||
{0x07,(0x08<<3)|0x0, {{0x61, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
|
||||
{0x02,(0x05<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
|
||||
{0x04,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x1, 0x0},
|
||||
{0x08,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x2, 0x0},
|
||||
{0x02,(0x0e<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include "chip.h"
|
||||
|
||||
struct chip_operations mainboard_dell_s2850_ops = {
|
||||
CHIP_NAME("Dell S2850")
|
||||
};
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,219 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
|
||||
void *smp_write_config_table(void *v)
|
||||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "DELL ";
|
||||
static const char productid[12] = "S2850 ";
|
||||
struct mp_config_table *mc;
|
||||
unsigned char bus_num;
|
||||
unsigned char bus_isa;
|
||||
unsigned char bus_pxhd_1;
|
||||
unsigned char bus_pxhd_2;
|
||||
unsigned char bus_pxhd_3;
|
||||
unsigned char bus_pxhd_4;
|
||||
unsigned char bus_ich5r_1;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
||||
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||
mc->mpc_spec = 0x04;
|
||||
mc->mpc_checksum = 0; /* not yet computed */
|
||||
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||
mc->mpc_oemptr = 0;
|
||||
mc->mpc_oemsize = 0;
|
||||
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||
mc->mpc_lapic = LAPIC_ADDR;
|
||||
mc->mpe_length = 0;
|
||||
mc->mpe_checksum = 0;
|
||||
mc->reserved = 0;
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
/* ich5r */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
|
||||
if (dev) {
|
||||
bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n");
|
||||
|
||||
bus_ich5r_1 = 7;
|
||||
bus_isa = 8;
|
||||
}
|
||||
/* pxhd-1 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
|
||||
if (dev) {
|
||||
bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:00.0, using defaults\n");
|
||||
|
||||
bus_pxhd_1 = 2;
|
||||
}
|
||||
/* pxhd-2 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
|
||||
if (dev) {
|
||||
bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:00.2, using defaults\n");
|
||||
|
||||
bus_pxhd_2 = 3;
|
||||
}
|
||||
|
||||
/* pxhd-3 */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x4,0));
|
||||
if (dev) {
|
||||
bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 0:04.0, using defaults\n");
|
||||
|
||||
bus_pxhd_3 = 5;
|
||||
}
|
||||
/* pxhd-4 */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
|
||||
if (dev) {
|
||||
bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 0:06.0, using defaults\n");
|
||||
|
||||
bus_pxhd_4 = 6;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* define bus and isa numbers */
|
||||
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
|
||||
smp_write_bus(mc, bus_num, "PCI ");
|
||||
}
|
||||
smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* IOAPIC handling */
|
||||
|
||||
smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
|
||||
{
|
||||
struct resource *res;
|
||||
device_t dev;
|
||||
/* pxhd apic 3 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x03, 0x20, res->base);
|
||||
}
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find IOAPIC PCI 1:00.1\n");
|
||||
}
|
||||
/* pxhd apic 4 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x04, 0x20, res->base);
|
||||
}
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find IOAPIC PCI 1:00.3\n");
|
||||
}
|
||||
}
|
||||
/* ISA backward compatibility interrupts */
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
bus_isa, 0x00, 0x02, 0x00);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
bus_isa, 0x01, 0x02, 0x01);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
bus_isa, 0x00, 0x02, 0x02);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
bus_isa, 0x03, 0x02, 0x03);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
bus_isa, 0x04, 0x02, 0x04);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x74, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
bus_isa, 0x06, 0x02, 0x06);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x76, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
bus_isa, 0x08, 0x02, 0x08);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
bus_isa, 0x09, 0x02, 0x09);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x77, 0x02, 0x17);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x75, 0x02, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
bus_isa, 0x0c, 0x02, 0x0c);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
bus_isa, 0x0d, 0x02, 0x0d);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
bus_isa, 0x0e, 0x02, 0x0e);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
bus_isa, 0x0f, 0x02, 0x0f);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x74, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x7c, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x7d, 0x02, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pxhd_1, 0x08, 0x03, 0x00);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pxhd_1, 0x0c, 0x03, 0x06);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pxhd_1, 0x0d, 0x03, 0x07);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pxhd_2, 0x08, 0x04, 0x00);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_ich5r_1, 0x04, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pxhd_4, 0x00, 0x02, 0x10);
|
||||
#if 0
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
(bus_isa - 1), 0x04, 0x02, 0x10);
|
||||
#endif
|
||||
/* Standard local interrupt assignments */
|
||||
#if 0
|
||||
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
bus_isa, 0x00, MP_APIC_ALL, 0x00);
|
||||
#endif
|
||||
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
bus_isa, 0x00, MP_APIC_ALL, 0x01);
|
||||
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
|
||||
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||
printk_debug("Wrote the mp table end at: %p - %p\n",
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
return smp_next_mpe_entry(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
#include <arch/io.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#ifndef __ROMCC__
|
||||
#include <device/device.h>
|
||||
#define PCI_ID(VENDOR_ID, DEVICE_ID) \
|
||||
((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
|
||||
#define PCI_DEV_INVALID 0
|
||||
|
||||
static inline device_t pci_locate_device(unsigned pci_id, device_t from)
|
||||
{
|
||||
return dev_find_device(pci_id >> 16, pci_id & 0xffff, from);
|
||||
}
|
||||
#endif
|
||||
|
||||
void soft_reset(void)
|
||||
{
|
||||
outb(0x04, 0xcf9);
|
||||
}
|
||||
void hard_reset(void)
|
||||
{
|
||||
outb(0x02, 0xcf9);
|
||||
outb(0x06, 0xcf9);
|
||||
}
|
||||
void full_reset(void)
|
||||
{
|
||||
device_t dev;
|
||||
/* Enable power on after power fail... */
|
||||
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_ISA), 0);
|
||||
if (dev != PCI_DEV_INVALID) {
|
||||
unsigned byte;
|
||||
byte = pci_read_config8(dev, 0xa4);
|
||||
byte &= 0xfe;
|
||||
pci_write_config8(dev, 0xa4, byte);
|
||||
|
||||
}
|
||||
outb(0x0e, 0xcf9);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
#include <arch/romcc_io.h>
|
||||
|
||||
static void mch_reset(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void mainboard_set_e7520_pll(unsigned bits)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
static void mainboard_set_e7520_leds(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
#include <device/pnp_def.h>
|
||||
|
||||
#define NSC_WD_DEV PNP_DEV(0x2e, 0xa)
|
||||
#define NSC_WDBASE 0x600
|
||||
#define ICH5_WDBASE 0x400
|
||||
#define ICH5_GPIOBASE 0x500
|
||||
|
||||
static void disable_sio_watchdog(device_t dev)
|
||||
{
|
||||
#if 0
|
||||
/* FIXME move me somewhere more appropriate */
|
||||
pnp_set_logical_device(dev);
|
||||
pnp_set_enable(dev, 1);
|
||||
pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE);
|
||||
/* disable the sio watchdog */
|
||||
outb(0, NSC_WDBASE + 0);
|
||||
pnp_set_enable(dev, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void disable_ich5_watchdog(void)
|
||||
{
|
||||
/* FIXME move me somewhere more appropriate */
|
||||
device_t dev;
|
||||
unsigned long value, base;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
|
||||
if (dev == PCI_DEV_INVALID) {
|
||||
die("Missing ich5?");
|
||||
}
|
||||
/* Enable I/O space */
|
||||
value = pci_read_config16(dev, 0x04);
|
||||
value |= (1 << 10);
|
||||
pci_write_config16(dev, 0x04, value);
|
||||
|
||||
/* Set and enable acpibase */
|
||||
pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
|
||||
pci_write_config8(dev, 0x44, 0x10);
|
||||
base = ICH5_WDBASE + 0x60;
|
||||
|
||||
/* Set bit 11 in TCO1_CNT */
|
||||
value = inw(base + 0x08);
|
||||
value |= 1 << 11;
|
||||
outw(value, base + 0x08);
|
||||
|
||||
/* Clear TCO timeout status */
|
||||
outw(0x0008, base + 0x04);
|
||||
outw(0x0002, base + 0x06);
|
||||
}
|
||||
|
||||
|
||||
static void disable_watchdogs(void)
|
||||
{
|
||||
// disable_sio_watchdog(NSC_WD_DEV);
|
||||
disable_ich5_watchdog();
|
||||
print_debug("Watchdogs disabled\r\n");
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue