soc/qualcomm/qcs405: Support for new SoC

Adding the basic infrastruture soc support for qcs405 and
a new build variant.

TEST=build

Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/soc/qualcomm/qcs405/Kconfig

@@ -0,0 +1,20 @@
+
+config SOC_QUALCOMM_QCS405
+	bool
+	default n
+	select ARCH_BOOTBLOCK_ARMV8_64
+	select ARCH_RAMSTAGE_ARMV8_64
+	select ARCH_ROMSTAGE_ARMV8_64
+	select ARCH_VERSTAGE_ARMV8_64
+	select BOOTBLOCK_CONSOLE
+	select GENERIC_GPIO_LIB
+	select GENERIC_UDELAY
+	select HAVE_MONOTONIC_TIMER
+
+if SOC_QUALCOMM_QCS405
+
+config VBOOT
+	select VBOOT_SEPARATE_VERSTAGE
+	select VBOOT_RETURN_FROM_VERSTAGE
+	select VBOOT_STARTS_IN_BOOTBLOCK
+endif

src/soc/qualcomm/qcs405/Makefile.inc

@@ -0,0 +1,32 @@
+
+ifeq ($(CONFIG_SOC_QUALCOMM_QCS405),y)
+
+################################################################################
+bootblock-y += bootblock.c
+bootblock-y += timer.c
+bootblock-y += spi.c
+
+################################################################################
+verstage-y += timer.c
+verstage-y += spi.c
+
+################################################################################
+romstage-y += timer.c
+romstage-y += spi.c
+romstage-y += cbmem.c
+
+################################################################################
+ramstage-y += soc.c
+ramstage-y += timer.c
+ramstage-y += spi.c
+ramstage-y += cbmem.c
+
+################################################################################
+
+CPPFLAGS_common += -Isrc/soc/qualcomm/qcs405/include
+
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
+	@printf "Generating: $(subst $(obj)/,,$(@))\n"
+	cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin
+
+endif

src/soc/qualcomm/qcs405/bootblock.c

@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+
+void bootblock_soc_init(void)
+{
+
+}

src/soc/qualcomm/qcs405/cbmem.c

@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+
+void *cbmem_top(void)
+{
+	return (void *)((uintptr_t)3 * GiB);
+}

src/soc/qualcomm/qcs405/include/soc/gpio.h

@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_QUALCOMM_QCS405_GPIO_H_
+#define _SOC_QUALCOMM_QCS405_GPIO_H_
+
+#include <types.h>
+
+typedef u32 gpio_t;
+
+#endif // _SOC_QUALCOMM_QCS405_GPIO_H_

src/soc/qualcomm/qcs405/include/soc/memlayout.ld

@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+
+/* SYSTEM_IMEM : 0x8600000 - 0x8607FFF */
+#define SSRAM_START(addr) SYMBOL(ssram, addr)
+#define SSRAM_END(addr) SYMBOL(essram, addr)
+
+/* BOOT_IMEM   : 0x8C00000 - 0x8D80000 */
+#define BSRAM_START(addr) SYMBOL(bsram, addr)
+#define BSRAM_END(addr) SYMBOL(ebsram, addr)
+
+SECTIONS
+{
+	SSRAM_START(0x8600000)
+	SSRAM_END(0x8608000)
+
+	BSRAM_START(0x8C00000)
+	OVERLAP_VERSTAGE_ROMSTAGE(0x8C00000, 100K)
+	REGION(fw_reserved2, 0x8C19000, 0x16000, 4096)
+	BOOTBLOCK(0x8C2F000, 40K)
+	TTB(0x8C39000, 56K)
+	VBOOT2_WORK(0x8C47000, 16K)
+	STACK(0x8C4B000, 16K)
+	TIMESTAMP(0x8C4F000, 1K)
+	PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K)
+	PRERAM_CBFS_CACHE(0x8C57400, 70K)
+	REGION(bsram_unused, 0x8C68C00, 0xA2400, 0x100)
+	BSRAM_END(0x8D80000)
+
+	DRAM_START(0x90000000)
+	POSTRAM_CBFS_CACHE(0x90000000, 384K)
+	RAMSTAGE(0x90800000, 128K)
+}

src/soc/qualcomm/qcs405/soc.c

@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <timestamp.h>
+
+static void soc_read_resources(struct device *dev)
+{
+
+}
+
+static void soc_init(struct device *dev)
+{
+
+}
+
+static struct device_operations soc_ops = {
+	.read_resources = soc_read_resources,
+	.init = soc_init,
+};
+
+static void enable_soc_dev(struct device *dev)
+{
+	dev->ops = &soc_ops;
+}
+
+struct chip_operations soc_qualcomm_qcs405_ops = {
+	CHIP_NAME("SOC Qualcomm QCS405")
+	.enable_dev = enable_soc_dev,
+};

src/soc/qualcomm/qcs405/spi.c

@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <spi-generic.h>
+#include <spi_flash.h>
+
+static int spi_ctrlr_claim_bus(const struct spi_slave *slave)
+{
+	return 0;
+}
+
+static void spi_ctrlr_release_bus(const struct spi_slave *slave)
+{
+
+}
+
+static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
+			  size_t bytes_out, void *din, size_t bytes_in)
+{
+	return 0;
+}
+
+static const struct spi_ctrlr spi_ctrlr = {
+	.claim_bus = spi_ctrlr_claim_bus,
+	.release_bus = spi_ctrlr_release_bus,
+	.xfer = spi_ctrlr_xfer,
+	.max_xfer_size = 65535,
+};
+
+const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
+	{
+		.ctrlr = &spi_ctrlr,
+		.bus_start = 0,
+		.bus_end = 0,
+	},
+};
+
+const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);

src/soc/qualcomm/qcs405/timer.c

@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <timer.h>
+#include <delay.h>
+
+void timer_monotonic_get(struct mono_time *mt)
+{
+
+}
+
+void init_timer(void)
+{
+
+}