lp4x: Add new memory parts and generate SPDs
This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for TGL and JSL: 1. MT53E512M32D2NP-046 WT:E 2. K4U6E3S4AA-MGCR 3. H9HCNNNCPMMLXR-NEE 4. K4UBE3D4AA-MGCR BUG=b:157862308, b:157732528 Change-Id: Ib7538247d39dfe5faab277d646f87f09103d6969 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41989 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -7,3 +7,7 @@ H9HKNNNCRMBVAR-NEH,spd-5.hex
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MT53E1G64D4SQ-046 WT:A,spd-6.hex
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MT53E512M32D2NP-046 WT:F,spd-1.hex
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NT6AP256T32AV-J2,spd-7.hex
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K4U6E3S4AA-MGCR,spd-1.hex
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MT53E512M32D2NP-046 WT:E,spd-1.hex
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H9HCNNNCPMMLXR-NEE,spd-3.hex
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K4UBE3D4AA-MGCR,spd-3.hex
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@ -7,3 +7,7 @@ H9HKNNNCRMBVAR-NEH,spd-1.hex
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MT53E1G64D4SQ-046 WT:A,spd-4.hex
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MT53E512M32D2NP-046 WT:F,spd-1.hex
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NT6AP256T32AV-J2,spd-5.hex
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K4U6E3S4AA-MGCR,spd-1.hex
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MT53E512M32D2NP-046 WT:E,spd-1.hex
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H9HCNNNCPMMLXR-NEE,spd-3.hex
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K4UBE3D4AA-MGCR,spd-3.hex
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@ -109,6 +109,54 @@
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"tckMaxPs": 1250,
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"casLatencies": "14 20 24 28 32"
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}
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}
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},
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{
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"name": "K4U6E3S4AA-MGCR",
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"attribs": {
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"densityPerChannelGb": 8,
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"banks": 8,
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"channelsPerDie": 2,
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"diesPerPackage": 1,
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"bitWidthPerChannel": 16,
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"ranksPerChannel": 1,
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"speedMbps": 4267
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}
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},
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{
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"name": "MT53E512M32D2NP-046 WT:E",
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"attribs": {
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"densityPerChannelGb": 8,
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"banks": 8,
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"channelsPerDie": 2,
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"diesPerPackage": 1,
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"bitWidthPerChannel": 16,
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"ranksPerChannel": 1,
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"speedMbps": 4267
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}
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},
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{
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"name": "H9HCNNNCPMMLXR-NEE",
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"attribs": {
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"densityPerChannelGb": 8,
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"banks": 8,
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"channelsPerDie": 2,
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"diesPerPackage": 2,
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"bitWidthPerChannel": 16,
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"ranksPerChannel": 2,
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"speedMbps": 4267
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}
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},
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{
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"name": "K4UBE3D4AA-MGCR",
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"attribs": {
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"densityPerChannelGb": 8,
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"banks": 8,
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"channelsPerDie": 2,
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"diesPerPackage": 2,
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"bitWidthPerChannel": 16,
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"ranksPerChannel": 2,
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"speedMbps": 4267
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}
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}
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]
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}
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