mb/google/brya: Move ACPI MPTS method from DSDT to SSDT for Brya and Redrix
This change is to move MPTS (Mainboard Prepare To Sleep) method from wwan_power.asl to SSDT. MPTS is mainboard-specific method, while wwan_power.asl is meant for WWAN from its name. Having fixed MPTS method (i.e. DSDT) can not cover the case where device only presents and certain CBI bit(s) is(are) set. In Redrix and Brya, there are SKUs with or without 5G, 4G device. For those with 4G, MPTS method should be different. For those with no WWAN device, no MPTS is needed. Having MPTS generating in SSDT also eliminates the need for introducing Kconfig flags to support different devices in the future. MPTS method is created inside mainboard_fill_ssdt function in which the corresponding variant function is called. This will generate the following for the mainboard: Scope (\_SB) { Method (MPTS, 1, Serialized) { Local0 = \_SB.PCI0.RP01.RTD3._STA () If ((Local0 == One)) { \_SB.PCI0.RP01.PXSX.DPTS (Arg0) } } } Test: Check the SSDT for MPTS method under \_SB after boot to OS Use shutdown command and check the GPIO pins from logical analyzer Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I0f0b7638e90a7862173fca99305398bb250373e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -36,8 +36,6 @@ config BOARD_GOOGLE_BRYA0
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select BOARD_GOOGLE_BASEBOARD_BRYA
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select DRIVERS_GENESYSLOGIC_GL9755
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select DRIVERS_INTEL_MIPI_CAMERA
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select HAVE_PCIE_WWAN
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select HAVE_WWAN_POWER_SEQUENCE
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select SOC_INTEL_COMMON_BLOCK_IPU
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select SOC_INTEL_CRASHLOG
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@ -46,8 +44,6 @@ config BOARD_GOOGLE_BRYA4ES
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select BOARD_GOOGLE_BASEBOARD_BRYA
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select DRIVERS_GENESYSLOGIC_GL9755
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select DRIVERS_INTEL_MIPI_CAMERA
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select HAVE_PCIE_WWAN
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select HAVE_WWAN_POWER_SEQUENCE
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select SOC_INTEL_COMMON_BLOCK_IPU
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select SOC_INTEL_CRASHLOG
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@ -118,8 +114,6 @@ config BOARD_GOOGLE_REDRIX
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select DRIVERS_I2C_MAX98390
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select DRIVERS_INTEL_MIPI_CAMERA
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select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
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select HAVE_PCIE_WWAN
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select HAVE_WWAN_POWER_SEQUENCE
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select SOC_INTEL_COMMON_BLOCK_IPU
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config BOARD_GOOGLE_REDRIX4ES
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@ -132,8 +126,6 @@ config BOARD_GOOGLE_REDRIX4ES
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select DRIVERS_I2C_MAX98390
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select DRIVERS_INTEL_MIPI_CAMERA
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select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
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select HAVE_PCIE_WWAN
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select HAVE_WWAN_POWER_SEQUENCE
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select SOC_INTEL_COMMON_BLOCK_IPU
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config BOARD_GOOGLE_TAEKO
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@ -5,6 +5,10 @@
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#include <ec/ec.h>
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#include <soc/ramstage.h>
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#include <fw_config.h>
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#include <acpi/acpigen.h>
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#include <drivers/wwan/fm/chip.h>
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WEAK_DEV_PTR(rp6_wwan);
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static void add_fw_config_oem_string(const struct fw_config *config, void *arg)
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{
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@ -55,10 +59,54 @@ static void mainboard_dev_init(struct device *dev)
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mainboard_ec_init();
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}
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static void mainboard_generate_shutdown(const struct device *dev)
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{
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const struct drivers_wwan_fm_config *config = config_of(dev);
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const struct device *parent = dev->bus->dev;
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if (!config)
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return;
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if (config->rtd3dev) {
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acpigen_write_store();
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acpigen_emit_namestring(acpi_device_path_join(parent, "RTD3._STA"));
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acpigen_emit_byte(LOCAL0_OP);
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acpigen_write_if_lequal_op_int(LOCAL0_OP, ONE_OP);
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{
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acpigen_emit_namestring(acpi_device_path_join(dev, "DPTS"));
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acpigen_emit_byte(ARG0_OP);
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}
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acpigen_write_if_end();
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} else {
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acpigen_emit_namestring(acpi_device_path_join(dev, "DPTS"));
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acpigen_emit_byte(ARG0_OP);
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}
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}
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static void mainboard_fill_ssdt(const struct device *dev)
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{
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const struct device *wwan = DEV_PTR(rp6_wwan);
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if (wwan) {
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acpigen_write_scope("\\_SB");
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acpigen_write_method_serialized("MPTS", 1);
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mainboard_generate_shutdown(wwan);
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acpigen_write_method_end(); /* Method */
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acpigen_write_scope_end(); /* Scope */
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}
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/* for variant to fill additional SSDT */
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variant_fill_ssdt(dev);
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}
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void __weak variant_fill_ssdt(const struct device *dev)
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{
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/* Add board-specific SSDT entries */
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}
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static void mainboard_enable(struct device *dev)
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{
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dev->ops->init = mainboard_dev_init;
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dev->ops->get_smbios_strings = mainboard_smbios_strings;
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dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
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}
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struct chip_operations mainboard_ops = {
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@ -23,6 +23,7 @@ void variant_get_spd_info(struct mem_spd *spd_info);
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int variant_memory_sku(void);
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bool variant_is_half_populated(void);
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void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config);
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void variant_fill_ssdt(const struct device *dev);
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/* Modify devictree settings during ramstage */
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void variant_devtree_update(void);
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@ -198,7 +198,7 @@ chip soc/intel/alderlake
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register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
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register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
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use rp6_rtd3 as rtd3dev
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device generic 0 on
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device generic 0 alias rp6_wwan on
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probe DB_LTE LTE_PCIE
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end
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end
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@ -195,7 +195,7 @@ chip soc/intel/alderlake
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register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
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register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
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use rp6_rtd3 as rtd3dev
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device generic 0 on
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device generic 0 alias rp6_wwan on
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probe DB_LTE LTE_PCIE
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end
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end
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@ -92,6 +92,7 @@ chip soc/intel/alderlake
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},
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}"
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register "tcc_offset" = "3" # TCC of 97C
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device domain 0 on
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device ref igpu on
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chip drivers/gfx/generic
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@ -178,7 +179,7 @@ chip soc/intel/alderlake
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register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
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register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
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use rp6_rtd3 as rtd3dev
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device generic 0 on
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device generic 0 alias rp6_wwan on
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probe DB_LTE LTE_PCIE
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end
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end
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@ -78,6 +78,7 @@ chip soc/intel/alderlake
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},
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}"
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register "tcc_offset" = "3" # TCC of 97C
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device domain 0 on
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device ref igpu on
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chip drivers/gfx/generic
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@ -164,7 +165,7 @@ chip soc/intel/alderlake
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register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
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register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
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use rp6_rtd3 as rtd3dev
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device generic 0 on
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device generic 0 alias rp6_wwan on
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probe DB_LTE LTE_PCIE
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end
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end
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