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Fix usb debug dongle support 

- move enable_usbdebug() declaration to usbdebug.h
- reinitialize debug driver in ramstage, as copying the data
  structure from romstage doesn't work right now. This way of copying
  data from romstage to ramstage is really board/cpu specific, and is
  likely to break often. So don't do it.

Change-Id: I394678ded6679c1803e29eb691b926182bdcab68
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/355
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Sven Schnelle 2011-10-30 09:57:35 +01:00 committed by Stefan Reinauer
parent 28f6a43755
commit 20fc631ad2
20 changed files with 34 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/console/console.c
View File

@ -30,6 +30,10 @@
#include <console/ne2k.h>
#endif
#if CONFIG_USBDEBUG
#include <usbdebug.h>
#endif
#ifndef __PRE_RAM__
#include <string.h>
#include <pc80/mc146818rtc.h>

10
src/console/usbdebug_console.c
View File

@ -50,15 +50,7 @@ unsigned get_ehci_debug(void)
static void dbgp_init(void)
{
struct ehci_debug_info *dbg_infox;
/* At this point, all we have to do is copy the fixed address
* debug_info data structure to our version defined above. */
dbg_infox = (struct ehci_debug_info *)
((CONFIG_RAMTOP) - sizeof(struct ehci_debug_info));
memcpy(&dbg_info, dbg_infox, sizeof(struct ehci_debug_info));
usbdebug_init(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, &dbg_info);
}
static void dbgp_tx_byte(unsigned char data)

3
src/include/ehci.h
View File

@ -25,6 +25,7 @@
#define EHCI_BAR_INDEX 0x10
#ifndef __ROMCC__
/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
/* Section 2.2 Host Controller Capability Registers */
@ -199,5 +200,5 @@ struct ehci_dbg_port {
u32 address;
#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
} __attribute__ ((packed));
#endif
#endif

5
src/include/usbdebug.h
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@ -32,6 +32,8 @@ struct ehci_debug_info {
u32 endpoint_in;
};
#ifndef __ROMCC__
void enable_usbdebug(unsigned int port);
int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size);
int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size);
void set_ehci_base(unsigned ehci_base);
@ -40,5 +42,6 @@ unsigned get_ehci_debug(void);
void set_debug_port(unsigned port);
int early_usbdebug_init(void);
void usbdebug_tx_byte(unsigned char data);
int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info);
#endif
#endif

1
src/lib/Makefile.inc
View File

@ -40,5 +40,6 @@ driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c
smm-y += memcpy.c cbfs.c memset.c memcmp.c
smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
smm-$(CONFIG_USBDEBUG) += usbdebug.c
$(obj)/lib/version.ramstage.o : $(obj)/build.h

6
src/lib/usbdebug.c
View File

@ -238,7 +238,6 @@ int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size)
dbg_info->endpoint_in, data, size);
}
#ifdef __PRE_RAM__
static void dbgp_mdelay(int ms)
{
int i;
@ -356,7 +355,7 @@ static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port)
}
static int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info)
int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info)
{
struct ehci_caps *ehci_caps;
struct ehci_regs *ehci_regs;
@ -566,8 +565,6 @@ next_debug_port:
return -10;
}
// **** This part is probably x86 specific and used by romstage.c **** //
int early_usbdebug_init(void)
{
struct ehci_debug_info *dbg_info = (struct ehci_debug_info *)
@ -588,4 +585,3 @@ void usbdebug_tx_byte(unsigned char data)
dbgp_bulk_write_x(dbg_info, (char*)&data, 1);
}
}
#endif

4
src/southbridge/amd/sb600/Makefile.inc
View File

@ -8,4 +8,6 @@ driver-y += hda.c
driver-y += ac97.c
driver-y += pci.c
ramstage-y += reset.c
romstage-y += enable_usbdebug.c
romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
smm-$(CONFIG_USBDEBUG) += enable_usbdebug.c

1
src/southbridge/amd/sb600/sb600.h
View File

@ -40,5 +40,4 @@ void sb600_enable(device_t dev);
void sb600_lpc_port80(void);
void sb600_pci_port80(void);
void enable_usbdebug(unsigned int port);
#endif /* SB600_H */

4
src/southbridge/amd/sb700/Makefile.inc
View File

@ -10,7 +10,9 @@ driver-y += pci.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
romstage-y += reset.c
ramstage-y += reset.c
romstage-y += enable_usbdebug.c
romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
smm-$(CONFIG_USBDEBUG) += enable_usbdebug.c
romstage-y += early_setup.c
romstage-y += smbus.c

2
src/southbridge/amd/sb700/sb700.h
View File

@ -82,8 +82,6 @@ int acpi_is_wakeup_early(void);
int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
void enable_usbdebug(unsigned int port);
u32 __attribute__ ((weak)) get_sbdn(u32 bus);
void __attribute__((weak)) enable_fid_change_on_sb(u32 sbbusn, u32 sbdn);
#endif /* SB700_H */

4
src/southbridge/amd/sb800/Makefile.inc
View File

@ -9,4 +9,6 @@ driver-y += pci.c
driver-y += pcie.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
ramstage-y += reset.c
romstage-y += enable_usbdebug.c
romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
smm-$(CONFIG_USBDEBUG) += enable_usbdebug.c

1
src/southbridge/amd/sb800/sb800.h
View File

@ -58,7 +58,6 @@ void sb800_clk_output_48Mhz(void);
int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
void enable_usbdebug(unsigned int port);
#else
void sb800_enable(device_t dev);
void __attribute__((weak)) sb800_setup_sata_phys(struct device *dev);

2
src/southbridge/intel/i82801gx/Makefile.inc
View File

@ -38,4 +38,6 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
romstage-y += early_smbus.c
romstage-$(CONFIG_USBDEBUG) += usb_debug.c
ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
smm-$(CONFIG_USBDEBUG) += usb_debug.c

1
src/southbridge/intel/i82801gx/i82801gx.h
View File

@ -46,7 +46,6 @@ extern void i82801gx_enable(device_t dev);
void enable_smbus(void);
int smbus_read_byte(unsigned device, unsigned address);
#endif
void enable_usbdebug(unsigned int port);
#endif
#define MAINBOARD_POWER_OFF 0

4
src/southbridge/nvidia/ck804/Makefile.inc
View File

@ -15,7 +15,9 @@ ramstage-y += reset.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
romstage-y += enable_usbdebug.c
romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
smm-$(CONFIG_USBDEBUG) += enable_usbdebug.c
romstage-y += early_smbus.c
chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc

1
src/southbridge/nvidia/ck804/ck804.h
View File

@ -24,7 +24,6 @@
#include "chip.h"
void ck804_enable(device_t dev);
void enable_usbdebug(unsigned int port);
extern struct pci_operations ck804_pci_ops;

4
src/southbridge/nvidia/mcp55/Makefile.inc
View File

@ -15,7 +15,9 @@ driver-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
ramstage-y += reset.c
romstage-y += enable_usbdebug.c
romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
smm-$(CONFIG_USBDEBUG) += enable_usbdebug.c
chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
chipset_bootblock_lds += $(src)/southbridge/nvidia/mcp55/romstrap.lds

1
src/southbridge/nvidia/mcp55/mcp55.h
View File

@ -35,7 +35,6 @@ extern struct pci_operations mcp55_pci_ops;
#else
#if !defined(__ROMCC__)
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
void enable_usbdebug(unsigned int port);
#endif
#endif

5
src/southbridge/sis/sis966/Makefile.inc
View File

@ -9,7 +9,10 @@ driver-y += sata.c
driver-y += pcie.c
driver-y += aza.c
ramstage-y += reset.c
romstage-y += enable_usbdebug.c
romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
smm-$(CONFIG_USBDEBUG) += enable_usbdebug.c
chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc
chipset_bootblock_lds += $(src)/southbridge/sis/sis966/romstrap.lds

4
src/southbridge/sis/sis966/sis966.h
View File

@ -39,8 +39,4 @@
void sis966_enable(device_t dev);
#endif
#if defined(__PRE_RAM__) && !defined(__ROMCC__)
void enable_usbdebug(unsigned int port);
#endif
#endif /* SIS966_H */