spare 4s for restart
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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63f2f721b4
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@ -42,10 +42,16 @@ static void soft_reset(void)
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set_bios_reset();
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set_bios_reset();
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pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
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pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
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}
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}
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#define AMD8111_RESET PCI_DEV( \
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HARD_RESET_BUS, \
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HARD_RESET_DEVICE, \
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HARD_RESET_FUNCTION)
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static void soft2_reset(void)
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static void soft2_reset(void)
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{
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{
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set_bios_reset();
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set_bios_reset();
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pci_write_config8(PCI_DEV(3, 0x04, 0), 0x47, 1);
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pci_write_config8(AMD8111_RESET, 0x47, 1);
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}
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}
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static void memreset_setup(void)
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static void memreset_setup(void)
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@ -139,7 +145,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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return smbus_read_byte(device, address);
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return smbus_read_byte(device, address);
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}
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}
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//#include "northbridge/amd/amdk8/setup_resource_map.c"
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#include "northbridge/amd/amdk8/setup_resource_map.c"
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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#include "sdram/generic_sdram.c"
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@ -204,6 +210,13 @@ static void main(unsigned long bist)
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#else
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#else
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/* cpu reset also reset the memtroller ????
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/* cpu reset also reset the memtroller ????
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need soft_reset to reset all except keep HT link freq and width */
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need soft_reset to reset all except keep HT link freq and width */
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/* So we don't need to
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1. jmp to __cpu_reset
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2. jmp to __main to copy ROM to ram (It costs some time)
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3. call hardwaremain(), it will according to boot_complete to issue hard_reset in southbridge.
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(Actually it is soft2_reset(); --- without call hard_reset, the memory is corrupted.
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We will call soft2_reset directly to spare time in 1 and 2 and 3.2
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*/
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distinguish_cpu_resets();
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distinguish_cpu_resets();
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soft2_reset();
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soft2_reset();
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#endif
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#endif
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