GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

google/glados: csme: program sml gpios for csme power gating 

For SMT controllers to power gate, all SMT/SMS clock, data and alert signals should be inactive.

The SML0 blocks are not used for any functional purposes and are not configured in the GPIO tables.
SMT hardware will not allow the blocks to be power gated in this scenario. The SML* pins are
now configured as GPIOs - input and deep.

With this change, the SMT blocks are properly power gating.

BRANCH=none
BUG=chrome-os-partner:45618
TEST=build for Glados.

Change-Id: Ie5406f2a1e0c485ac1290e2154755085fa3bb7b9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5b3fe3c2ddea4c5daedb04078b24cff14efa49d5
Original-Change-Id: I8dcc0bfc121e612a174e6fe3152650d0fcd68f39
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/306481
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12160
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Archana Patni 2015-10-08 01:43:47 +05:30 committed by Patrick Georgi
parent f969d4a5ef
commit 20ffe1944c
1 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/mainboard/google/glados/gpio.h
View File

@ -100,15 +100,15 @@ static const struct pad_config gpio_table[] = {
/* GSPI1_CLK */ /* GPP_B20 */ /* GSPI1_CLK */ /* GPP_B20 */
/* GSPI1_MISO */ /* GPP_B21 */ /* GSPI1_MISO */ /* GPP_B21 */
/* GSPI1_MOSI */ /* GPP_B22 */ /* GSPI1_MOSI */ /* GPP_B22 */
/* SM1ALERT# */ /* GPP_B23 */ /* SM1ALERT# */ PAD_CFG_GPO(GPP_B23, 0, DEEP),
/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */ /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */
/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */
/* SMBALERT# */ /* GPP_C2 */ /* SMBALERT# */ /* GPP_C2 */
/* SML0CLK */ /* GPP_C3 */ /* SML0CLK */ PAD_CFG_GPI(GPP_C3, NONE, DEEP),
/* SML0DATA */ /* GPP_C4 */ /* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP),
/* SML0ALERT# */ /* GPP_C5 */ /* SML0ALERT# */ PAD_CFG_GPO(GPP_C5, 0, DEEP),
/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ /* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
/* SM1DATA */ /* GPP_C7 */ /* SM1DATA */ PAD_CFG_GPI(GPP_C7, NONE, DEEP),
/* UART0_RXD */ /* GPP_C8 */ /* UART0_RXD */ /* GPP_C8 */
/* UART0_TXD */ /* GPP_C9 */ /* UART0_TXD */ /* GPP_C9 */
/* UART0_RTS# */ /* GPP_C10 */ /* UART0_RTS# */ /* GPP_C10 */