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rockchip/rk3288: Split free SRAM more evenly between stages 

When CB:33068 disabled the bootblock console on RK3288, it saved a
whooping 7K of SRAM, but it didn't readjust the stage boundaries to
spread that bounty evenly. This patch moves 4K of free space from the
bootblock to verstage/romstage to allow for future expansion.

Change-Id: I68a09ba80bde0d4f17fba1f7b38c63b7cf2a4672
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Julius Werner 2019-11-13 11:28:27 -08:00 committed by Patrick Georgi
parent dd0dc1ac92
commit 211792feab
1 changed files with 4 additions and 4 deletions
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8
src/soc/rockchip/rk3288/include/soc/memlayout.ld
View File

@ -30,10 +30,10 @@ SECTIONS
SRAM_START(0xFF700000) SRAM_START(0xFF700000)
TTB(0xFF700000, 16K) TTB(0xFF700000, 16K)
BOOTBLOCK(0xFF704004, 20K - 4) BOOTBLOCK(0xFF704004, 16K - 4)
PRERAM_CBMEM_CONSOLE(0xFF709000, 2K) PRERAM_CBMEM_CONSOLE(0xFF708000, 2K)
VBOOT2_WORK(0xFF709800, 12K) VBOOT2_WORK(0xFF708800, 12K)
OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 42K + 768) OVERLAP_VERSTAGE_ROMSTAGE(0xFF70B800, 46K + 768)
PRERAM_CBFS_CACHE(0xFF717300, 256) PRERAM_CBFS_CACHE(0xFF717300, 256)
TIMESTAMP(0xFF717400, 0x180) TIMESTAMP(0xFF717400, 0x180)
STACK(0xFF717580, 3K - 0x180) STACK(0xFF717580, 3K - 0x180)