armv7/snow: get to romstage
This patch does a few things to get us into romstage: - Add romstage as a stage (a later patch adds it as a binary, which is probably wrong). The Makefile magic is complex enough that we let it build the XIP file for now, but we no longer use it. - Replace findstage with loadstage. Loadstage will find a stage, load the code to memory, and zero the remaining part of memory. Now we can link the romstage to go anywhere! - Eliminate magic offsets from code/ldscripts and centralize Kconfig variables in src/cpu/samsung/exynos5250/Kconfig. - Tidy up code and serial output Change-Id: Iae4d2f9e7f429cb1df15d49daf9a08b88d75d79d Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2174 Tested-by: build bot (Jenkins)
This commit is contained in:
David Hendricks
Ronald G. Minnich
parent
f572e1e5fc
commit
211a5d56db
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@ -215,9 +215,8 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL
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@printf " CBFS $(subst $(obj)/,,$(@))\n"
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cp $(obj)/coreboot.pre1 $@.tmp
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$(CBFSTOOL) $@.tmp add-stage \
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-f $(objcbfs)/romstage_xip.elf \
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-n $(CONFIG_CBFS_PREFIX)/romstage -c none \
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-b $(shell cat $(objcbfs)/base_xip.txt)
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-f $(objcbfs)/romstage_null.debug \
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-n $(CONFIG_CBFS_PREFIX)/romstage -c none
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mv $@.tmp $@
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################################################################################
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@ -92,4 +92,4 @@ wait_for_interrupt:
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*/
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.align 2
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.Stack:
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.word CONFIG_SYS_INIT_SP_ADDR
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.word CONFIG_IRAM_STACK
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@ -39,12 +39,13 @@ void main(unsigned long bist)
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unsigned long entry;
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if (boot_cpu()) {
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bootblock_mainboard_init();
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bootblock_cpu_init();
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bootblock_mainboard_init();
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}
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entry = findstage(target1);
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printk(BIOS_INFO, "bootblock main(): loading romstage\n");
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entry = loadstage(target1);
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printk(BIOS_INFO, "bootblock main(): jumping to romstage\n");
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if (entry) call(entry);
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hlt();
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}
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@ -26,42 +26,93 @@
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#include <arch/byteorder.h>
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#include <arch/cbfs.h>
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static int cbfs_check_magic(struct cbfs_file *file)
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{
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return !strcmp(file->magic, CBFS_FILE_MAGIC) ? 1 : 0;
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return strcmp(file->magic, CBFS_FILE_MAGIC) ? 0 : 1;
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}
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static unsigned long findstage(const char* target)
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static unsigned long loadstage(const char* target)
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{
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unsigned long offset, align;
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struct cbfs_header *header = (struct cbfs_header *)(CONFIG_BOOTBLOCK_BASE + 0x40);
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/* FIXME: magic offsets */
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struct cbfs_header *header = (struct cbfs_header *)(0x02023400 + 0x40);
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// if (ntohl(header->magic) != CBFS_HEADER_MAGIC)
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// printk(BIOS_ERR, "ERROR: No valid CBFS header found!\n");
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offset = ntohl(header->offset);
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align = ntohl(header->align);
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printk(BIOS_INFO, "cbfs header (0x%p)\n", header);
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printk(BIOS_INFO, "\tmagic: 0x%08x\n", ntohl(header->magic));
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printk(BIOS_INFO, "\tversion: 0x%08x\n", ntohl(header->version));
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printk(BIOS_INFO, "\tromsize: 0x%08x\n", ntohl(header->romsize));
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printk(BIOS_INFO, "\tbootblocksize: 0x%08x\n", ntohl(header->bootblocksize));
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printk(BIOS_INFO, "\talign: 0x%08x\n", ntohl(header->align));
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printk(BIOS_INFO, "\toffset: 0x%08x\n", ntohl(header->offset));
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while(1) {
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struct cbfs_file *file;
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file = (struct cbfs_file *)(offset + CONFIG_ROMSTAGE_BASE);
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if (!cbfs_check_magic(file))
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struct cbfs_stage *stage;
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/* FIXME: SPI image hack */
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file = (struct cbfs_file *)(offset + CONFIG_SPI_IMAGE_HACK);
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if (!cbfs_check_magic(file)) {
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printk(BIOS_INFO, "magic is wrong, file: %p\n", file);
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return 0;
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if (!strcmp(CBFS_NAME(file), target))
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return (unsigned long)CBFS_SUBHEADER(file);
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}
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if (!strcmp(CBFS_NAME(file), target)) {
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uint32_t load, entry;
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printk(BIOS_INFO, "CBFS name matched, offset: %p\n", file);
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printk(BIOS_INFO, "\tmagic: %02x%02x%02x%02x%02x%02x%02x%02x\n",
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file->magic[0], file->magic[1], file->magic[2], file->magic[3],
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file->magic[4], file->magic[5], file->magic[6], file->magic[7]);
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printk(BIOS_INFO, "\tlen: 0x%08x\n", ntohl(file->len));
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printk(BIOS_INFO, "\ttype: 0x%08x\n", ntohl(file->type));
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printk(BIOS_INFO, "\tchecksum: 0x%08x\n", ntohl(file->checksum));
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printk(BIOS_INFO, "\toffset: 0x%08x\n", ntohl(file->offset));
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/* exploit the fact that this is all word-aligned. */
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stage = CBFS_SUBHEADER(file);
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load = stage->load;
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entry = stage->entry;
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int i;
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u32 *to = (void *)load;
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u32 *from = (void *)((u8 *)stage+sizeof(*stage));
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/* we could do memmove/memset here. But the math gets messy.
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* far easier just to do what we want.
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*/
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printk(BIOS_INFO, "entry: 0x%08x, load: 0x%08x, "
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"len: 0x%08x, memlen: 0x%08x\n", entry,
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load, stage->len, stage->memlen);
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for(i = 0; i < stage->len; i += 4)
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*to++ = *from++;
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for(; i < stage->memlen; i += 4)
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*to++ = 0;
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return entry;
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}
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int flen = ntohl(file->len);
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int foffset = ntohl(file->offset);
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unsigned long oldoffset = offset;
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offset = ALIGN(offset + foffset + flen, align);
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printk(BIOS_INFO, "offset: 0x%08lx\n", offset);
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if (offset <= oldoffset)
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return 0;
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if (offset < CONFIG_ROMSTAGE_BASE + ntohl(header->romsize));
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if (offset > CONFIG_ROMSTAGE_SIZE)
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return 0;
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}
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}
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static inline void call(unsigned long addr)
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{
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void (*doit)(void) = (void *)addr;
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__attribute__((noreturn)) void (*doit)(void) = (void *)addr;
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printk(BIOS_INFO, "addr: %08lx, doit: %p\n", addr, doit);
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/* FIXME: dumping SRAM content for sanity checking */
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int i;
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for (i = 0; i < 128; i++) {
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if (i % 16 == 0)
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printk(BIOS_INFO, "\n0x%08lx: ", addr + i);
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else
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printk(BIOS_INFO, " ");
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printk(BIOS_INFO, "%02x", *(uint8_t *)(addr + i));
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}
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/* FIXME: do we need to change to/from arm/thumb? */
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doit();
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}
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#endif
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@ -4,7 +4,6 @@
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static inline __attribute__((always_inline)) void hlt(void)
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{
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for (;;) ;
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//asm("hlt");
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}
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#endif /* ARCH_HLT_H */
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@ -1,6 +1,5 @@
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SECTIONS {
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/* FIXME: determine a sensible location... */
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. = (0x2026400);
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. = CONFIG_ID_SECTION_BASE;
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.id (.): {
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*(.id)
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}
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@ -24,22 +24,16 @@
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INCLUDE ldoptions
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*/
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/*
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* FIXME: what exactly should these be? maybe defined on a per-CPU basis?
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* FIXME 2: Somehow linker didn't like CONFIG_SPL_MAX_SIZE and CONFIG_SPL_TEXT_BASE...
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*/
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/* MEMORY { .sram : ORIGIN = 0x02023400, LENGTH = 0x3800 } */
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/*MEMORY { .sram : ORIGIN = 0x02023400, LENGTH = 0x10000 }*/
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/* We use ELF as output format. So that we can debug the code in some form. */
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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/* ENTRY(_start) */
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ENTRY(_start)
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SECTIONS
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{
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. = 0x02023400 + 0x4000;
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/* TODO make this a configurable option (per chipset). */
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. = CONFIG_ROMSTAGE_BASE;
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.romtext . : {
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_rom = .;
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@ -14,27 +14,16 @@ config SATA_AHCI
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bool
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default n
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config SPL_BUILD
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bool
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default n
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config SYS_TEXT_BASE
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hex "Executable code section"
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default 0x43e00000
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config SYS_SDRAM_BASE
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hex "SDRAM base address"
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default 0x40000000
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#FIXME(dhendrix, reinauer): re-visit this RAMBASE/RAMTOP stuff...
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config RAMBASE
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hex
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default SYS_SDRAM_BASE
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# according to stefan, this is RAMBASE + 1M.
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config RAMTOP
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hex
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default 0x40100000
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# Example SRAM/iRAM map for Exynos5250 platform:
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#
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# 0x0202_0000: vendor-provided BL1
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# 0x0202_3400: bootblock, assume up to 32KB in size
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# 0x0202_2600: ID section, assume 2KB in size. This will be
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# within the bootblock section.
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# 0x0203_0000: romstage, assume up to 128KB in size.
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# 0x0207_7f00: stack pointer
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# this may be used to calculate offsets
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config IRAM_BOTTOM
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hex
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default 0x02020000
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@ -43,14 +32,54 @@ config IRAM_TOP
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hex
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default 0x02077fff
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config SYS_INIT_SP_ADDR
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config BOOTBLOCK_BASE
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hex
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default 0x02058000
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default 0x02023400
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config ID_SECTION_BASE
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hex
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default 0x02026000
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config ROMSTAGE_BASE
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hex
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default 0x02030000
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config ROMSTAGE_SIZE
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hex
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default 0x10000
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# FIXME: This is for copying SPI content into SRAM temporarily and
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# will be removed when we have the SPI streaming driver implemented.
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config SPI_IMAGE_HACK
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hex
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default 0x02060000
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config IRAM_STACK
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hex
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default SYS_INIT_SP_ADDR
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default 0x02077f00
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# FIXME: other magic numbers that should probably go away
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config XIP_ROM_SIZE
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hex "ROM stage (BL2) size"
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default 0x20000
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hex
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default ROMSTAGE_SIZE
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config SYS_SDRAM_BASE
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hex "SDRAM base address"
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default 0x40000000
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config SPL_BUILD
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bool
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default n
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config SYS_TEXT_BASE
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hex "Executable code section"
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default 0x43e00000
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config RAMBASE
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hex
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default SYS_SDRAM_BASE
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# according to stefan, this is RAMBASE + 1M.
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config RAMTOP
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hex
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default 0x40100000
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@ -36,5 +36,6 @@ static int config_branch_prediction(int set_cr_z)
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void bootblock_cpu_init(void);
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void bootblock_cpu_init(void)
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{
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/* FIXME: this is a stub for now */
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volatile unsigned long *pshold = (unsigned long *)0x1004330c;
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*pshold |= 0x100;
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}
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@ -60,29 +60,6 @@ config BOOTBLOCK_MAINBOARD_INIT
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string
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default "mainboard/google/snow/bootblock.c"
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# SPL (second-phase loader) stuff
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config SPL_TEXT_BASE
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hex
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default 0x02023400
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help
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Location of SPL. Default location is within iRAM region.
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config ROMSTAGE_BASE
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hex
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default SPL_TEXT_BASE
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# FIXME: increased "SPL" size to get around build issues
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#config SPL_MAX_SIZE
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# hex "SPL executable max size"
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# default 0x3800
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# help
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# Max size of SPL. Default is 14KB
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config SPL_MAX_SIZE
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hex
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default 0x8000
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help
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Max size of SPL. Let's say 32KB for now...
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config DRAM_SIZE_MB
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int
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default 2048
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@ -42,8 +42,6 @@
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#define EXYNOS5_CLOCK_BASE 0x10010000
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volatile unsigned long *pshold = (unsigned long *)0x1004330c;
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/* FIXME(dhendrix): Can we move this SPI stuff elsewhere? */
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static void spi_rx_tx(struct exynos_spi *regs, int todo,
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void *dinp, void const *doutp, int i)
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@ -723,6 +721,9 @@ static void exynos5_uart_tx_byte(unsigned char data)
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// struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
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struct s5p_uart *uart = (struct s5p_uart *)uart3_base;
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if (data == '\n')
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exynos5_uart_tx_byte('\r');
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/* wait for room in the tx FIFO */
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while ((readl(uart->ufstat) & TX_FIFO_FULL_MASK)) {
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if (exynos5_uart_err_check(1))
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@ -738,12 +739,13 @@ void puts(const char *s)
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int n = 0;
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while (*s) {
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if (*s == '\n') {
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exynos5_uart_tx_byte(0xd); /* CR */
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}
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exynos5_uart_tx_byte(*s++);
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n++;
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}
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exynos5_uart_tx_byte(0xd); /* CR */
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exynos5_uart_tx_byte(0xa); /* LF */
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}
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static void do_serial(void)
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@ -2137,10 +2139,26 @@ void bootblock_mainboard_init(void)
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power_init();
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clock_init();
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do_serial();
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printk(BIOS_INFO, "%s: hello world\n", __func__);
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printk(BIOS_INFO, "%s: UART initialized\n", __func__);
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/* Copy romstage data from SPI ROM to SRAM */
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/* FIXME: test with something benign, then fix the offsets once
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we're more confident in this */
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copy_romstage(0x2000, 0x2060000, 0x800);
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printk(BIOS_INFO, "Copying romstage:\n"
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"\tSPI offset: 0x%06x\n"
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"\tiRAM offset: 0x%08x\n"
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"\tSize: 0x%x\n",
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0, CONFIG_SPI_IMAGE_HACK, CONFIG_ROMSTAGE_SIZE);
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copy_romstage(0x0, CONFIG_SPI_IMAGE_HACK, CONFIG_ROMSTAGE_SIZE);
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#if 0
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/* FIXME: dump SRAM content for sanity checking */
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uint32_t u;
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for (u = CONFIG_SPI_IMAGE_HACK; u < CONFIG_SPI_IMAGE_HACK + 128; u++) {
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if (u % 16 == 0)
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printk(BIOS_INFO, "\n0x%08x: ", u);
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else
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printk(BIOS_INFO, " ");
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printk(BIOS_INFO, "%02x", *(uint8_t *)(u));
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}
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printk(BIOS_INFO, "\n");
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#endif
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printk(BIOS_INFO, "%s: finished\n", __func__);
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}
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@ -21,6 +21,22 @@
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#include <system.h>
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#include <cache.h>
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#if 0
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#include <arch/io.h>
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/* FIXME: make i2c.h use standard types */
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#define uchar unsigned char
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#define uint unsigned int
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#include <device/i2c.h>
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#include <cpu/samsung/s5p-common/s3c24x0_i2c.h>
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#include "cpu/samsung/exynos5250/dmc.h"
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#include <cpu/samsung/exynos5250/power.h>
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#include <cpu/samsung/exynos5250/clock_init.h>
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#include <cpu/samsung/exynos5-common/uart.h>
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#endif
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#include <console/console.h>
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static void mmu_setup(void)
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{
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dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024);
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@ -29,5 +45,14 @@ static void mmu_setup(void)
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void main(void);
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void main(void)
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{
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// volatile unsigned long *pshold = (unsigned long *)0x1004330c;
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// i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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// power_init();
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// clock_init();
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// exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
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console_init();
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printk(BIOS_INFO, "hello from romstage\n");
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// *pshold &= ~0x100; /* shut down */
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mmu_setup();
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}
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