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soc/intel/cmn/{block, pch}: Migrate GPMR driver 

This patch migrates GPMR driver over DMI to accommodate future SOCs
with different interface (other than PCR/DMI).

TEST=Able to build and boot google/redrix.

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I00ac667e8d3f2ccefd8d51a8150a989fc8e5c7e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Subrata Banik 2022-04-13 12:13:09 +05:30 committed by Felix Held
parent d85e5eb287
commit 211be9c031
5 changed files with 23 additions and 38 deletions
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4
src/soc/intel/common/block/fast_spi/fast_spi.c
View File

@ -11,8 +11,8 @@
#include <commonlib/helpers.h> #include <commonlib/helpers.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <fast_spi_def.h> #include <fast_spi_def.h>
#include <intelblocks/dmi.h>
#include <intelblocks/fast_spi.h> #include <intelblocks/fast_spi.h>
#include <intelblocks/gpmr.h>
#include <lib.h> #include <lib.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <spi_flash.h> #include <spi_flash.h>
@ -342,7 +342,7 @@ static void fast_spi_enable_ext_bios(void)
#endif #endif
/* Configure Source decode for Extended BIOS Region */ /* Configure Source decode for Extended BIOS Region */
if (dmi_enable_gpmr(CONFIG_EXT_BIOS_WIN_BASE, CONFIG_EXT_BIOS_WIN_SIZE, if (enable_gpmr(CONFIG_EXT_BIOS_WIN_BASE, CONFIG_EXT_BIOS_WIN_SIZE,
soc_get_spi_psf_destination_id()) == CB_ERR) soc_get_spi_psf_destination_id()) == CB_ERR)
return; return;

25
src/soc/intel/common/block/gpmr/gpmr.c
View File

@ -1,21 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h> #include <console/console.h>
#include <intelblocks/dmi.h>
#include <intelblocks/gpmr.h> #include <intelblocks/gpmr.h>
#include <intelblocks/pcr.h> #include <intelblocks/pcr.h>
#include <soc/pcr_ids.h> #include <soc/pcr_ids.h>
#define MAX_GPMR_REGS 3
#define GPMR_OFFSET(x) (0x277c + (x) * 8)
#define DMI_PCR_GPMR_LIMIT_MASK 0xffff0000
#define DMI_PCR_GPMR_BASE_SHIFT 16
#define DMI_PCR_GPMR_BASE_MASK 0xffff
#define GPMR_DID_OFFSET(x) (0x2780 + (x) * 8)
#define DMI_PCR_GPMR_EN BIT(31)
/* GPMR Register read given offset */ /* GPMR Register read given offset */
uint32_t gpmr_read32(uint16_t offset) uint32_t gpmr_read32(uint16_t offset)
{ {
@ -41,7 +30,7 @@ static int get_available_gpmr(void)
for (i = 0; i < MAX_GPMR_REGS; i++) { for (i = 0; i < MAX_GPMR_REGS; i++) {
val = gpmr_read32(GPMR_DID_OFFSET(i)); val = gpmr_read32(GPMR_DID_OFFSET(i));
if (!(val & DMI_PCR_GPMR_EN)) if (!(val & GPMR_EN))
return i; return i;
} }
printk(BIOS_ERR, "%s: No available free gpmr found\n", __func__); printk(BIOS_ERR, "%s: No available free gpmr found\n", __func__);
@ -49,12 +38,12 @@ static int get_available_gpmr(void)
} }
/* Configure GPMR for the given base and size of extended BIOS Region */ /* Configure GPMR for the given base and size of extended BIOS Region */
enum cb_err dmi_enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id) enum cb_err enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id)
{ {
int gpmr_num; int gpmr_num;
uint32_t limit; uint32_t limit;
if (base & ~(DMI_PCR_GPMR_BASE_MASK << DMI_PCR_GPMR_BASE_SHIFT)) { if (base & ~(GPMR_BASE_MASK << GPMR_BASE_SHIFT)) {
printk(BIOS_ERR, "base is not 64-KiB aligned!\n"); printk(BIOS_ERR, "base is not 64-KiB aligned!\n");
return CB_ERR; return CB_ERR;
} }
@ -66,7 +55,7 @@ enum cb_err dmi_enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id)
return CB_ERR; return CB_ERR;
} }
if ((limit & ~DMI_PCR_GPMR_LIMIT_MASK) != 0xffff) { if ((limit & ~GPMR_LIMIT_MASK) != 0xffff) {
printk(BIOS_ERR, "limit does not end on a 64-KiB boundary!\n"); printk(BIOS_ERR, "limit does not end on a 64-KiB boundary!\n");
return CB_ERR; return CB_ERR;
} }
@ -77,11 +66,11 @@ enum cb_err dmi_enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id)
return CB_ERR; return CB_ERR;
/* Program Range for the given decode window */ /* Program Range for the given decode window */
gpmr_write32(GPMR_OFFSET(gpmr_num), (limit & DMI_PCR_GPMR_LIMIT_MASK) | gpmr_write32(GPMR_OFFSET(gpmr_num), (limit & GPMR_LIMIT_MASK) |
((base >> DMI_PCR_GPMR_BASE_SHIFT) & DMI_PCR_GPMR_BASE_MASK)); ((base >> GPMR_BASE_SHIFT) & GPMR_BASE_MASK));
/* Program source decode enable bit and the Destination ID */ /* Program source decode enable bit and the Destination ID */
gpmr_write32(GPMR_DID_OFFSET(gpmr_num), dest_id | DMI_PCR_GPMR_EN); gpmr_write32(GPMR_DID_OFFSET(gpmr_num), dest_id | GPMR_EN);
return CB_SUCCESS; return CB_SUCCESS;
} }

11
src/soc/intel/common/block/lpc/lpc_lib.c
View File

@ -7,6 +7,7 @@
#include <console/console.h> #include <console/console.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <intelblocks/gpmr.h>
#include <intelblocks/itss.h> #include <intelblocks/itss.h>
#include <intelblocks/lpc_lib.h> #include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h> #include <intelblocks/pcr.h>
@ -25,7 +26,7 @@ uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables)
io_enables |= reg_io_enables; io_enables |= reg_io_enables;
pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, io_enables); pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, io_enables);
if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); gpmr_write32(GPMR_LPCIOE, io_enables);
return io_enables; return io_enables;
} }
@ -43,7 +44,7 @@ uint16_t lpc_set_fixed_io_ranges(uint16_t io_ranges, uint16_t mask)
io_ranges |= reg_io_ranges & mask; io_ranges |= reg_io_ranges & mask;
pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, io_ranges); pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, io_ranges);
if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
pcr_write16(PID_DMI, PCR_DMI_LPCIOD, io_ranges); gpmr_write32(GPMR_LPCIOD, io_ranges);
return io_ranges; return io_ranges;
} }
@ -113,7 +114,7 @@ void lpc_open_pmio_window(uint16_t base, uint16_t size)
pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir); pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir);
if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1 + lgir_reg_num * 4, lgir); gpmr_write32(GPMR_LPCLGIR1 + lgir_reg_num * 4, lgir);
printk(BIOS_DEBUG, printk(BIOS_DEBUG,
"LPC: Opened IO window LGIR%d: base %llx size %x\n", "LPC: Opened IO window LGIR%d: base %llx size %x\n",
@ -148,7 +149,7 @@ void lpc_open_mmio_window(uintptr_t base, size_t size)
pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE, lgmr); pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE, lgmr);
if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
pcr_write32(PID_DMI, PCR_DMI_LPCGMR, lgmr); gpmr_write32(GPMR_LPCGMR, lgmr);
} }
/* /*
@ -249,7 +250,7 @@ static void lpc_set_gen_decode_range(
for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) { for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i), gen_io_dec[i]); pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i), gen_io_dec[i]);
if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1 + i * 4, gen_io_dec[i]); gpmr_write32(GPMR_LPCLGIR1 + i * 4, gen_io_dec[i]);
} }
} }

11
src/soc/intel/common/block/smbus/tco.c
View File

@ -7,6 +7,7 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <intelblocks/gpmr.h>
#include <intelblocks/pcr.h> #include <intelblocks/pcr.h>
#include <intelblocks/pmclib.h> #include <intelblocks/pmclib.h>
#include <intelblocks/tco.h> #include <intelblocks/tco.h>
@ -16,10 +17,6 @@
#include <soc/pm.h> #include <soc/pm.h>
#include <soc/smbus.h> #include <soc/smbus.h>
#define PCR_DMI_TCOBASE 0x2778
/* Enable TCO I/O range decode. */
#define TCOEN (1 << 1)
/* SMBUS TCO base address. */ /* SMBUS TCO base address. */
#define TCOBASE 0x50 #define TCOBASE 0x50
#define TCOCTL 0x54 #define TCOCTL 0x54
@ -122,10 +119,8 @@ static void tco_enable_bar(void)
/* Enable TCO in SMBUS */ /* Enable TCO in SMBUS */
pci_write_config32(dev, TCOCTL, reg32 | TCO_BASE_EN); pci_write_config32(dev, TCOCTL, reg32 | TCO_BASE_EN);
/* /* Program TCO Base Address */
* Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] gpmr_write32(GPMR_TCOBASE, tcobase | GPMR_TCOEN);
*/
pcr_write32(PID_DMI, PCR_DMI_TCOBASE, tcobase | TCOEN);
} }
/* /*

10
src/soc/intel/common/pch/lockdown/lockdown.c
View File

@ -2,10 +2,10 @@
#include <bootstate.h> #include <bootstate.h>
#include <intelblocks/cfg.h> #include <intelblocks/cfg.h>
#include <intelblocks/dmi.h>
#include <intelblocks/fast_spi.h> #include <intelblocks/fast_spi.h>
#include <intelblocks/pcr.h> #include <intelblocks/pcr.h>
#include <intelpch/lockdown.h> #include <intelpch/lockdown.h>
#include <intelblocks/gpmr.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/pcr_ids.h> #include <soc/pcr_ids.h>
#include <soc/soc_chip.h> #include <soc/soc_chip.h>
@ -25,7 +25,7 @@ int get_lockdown_config(void)
return common_config->chipset_lockdown; return common_config->chipset_lockdown;
} }
static void dmi_lockdown_cfg(void) static void lockdown_cfg(void)
{ {
/* /*
* GCS reg of DMI * GCS reg of DMI
@ -37,13 +37,13 @@ static void dmi_lockdown_cfg(void)
* "0b": SPI * "0b": SPI
* "1b": LPC/eSPI * "1b": LPC/eSPI
*/ */
pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); gpmr_or32(GPMR_GCS, GPMR_GCS_BILD);
/* /*
* Set Secure Register Lock (SRL) bit in DMI control register to lock * Set Secure Register Lock (SRL) bit in DMI control register to lock
* DMI configuration. * DMI configuration.
*/ */
pcr_or32(PID_DMI, PCR_DMI_DMICTL, PCR_DMI_DMICTL_SRLOCK); gpmr_or32(GPMR_DMICTL, GPMR_DMICTL_SRLOCK);
} }
static void fast_spi_lockdown_cfg(int chipset_lockdown) static void fast_spi_lockdown_cfg(int chipset_lockdown)
@ -94,7 +94,7 @@ static void platform_lockdown_config(void *unused)
fast_spi_lockdown_cfg(chipset_lockdown); fast_spi_lockdown_cfg(chipset_lockdown);
/* DMI lock down configuration */ /* DMI lock down configuration */
dmi_lockdown_cfg(); lockdown_cfg();
/* SoC lock down configuration */ /* SoC lock down configuration */
soc_lockdown_config(chipset_lockdown); soc_lockdown_config(chipset_lockdown);