This is part of the outstanding mcp55 commit from January 18th. It will
likely break the build, since it is only a small part, but it needs to go in at some point and doing it directory by directory makes things easier. Signed-off-by: Yinghai Lu <yinghai.lu at amd.com> Signed-off-by: Ed Swierk <eswierk at arastra.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ward Vandewege <ward at gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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778a42b129
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21332b80d0
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@ -67,5 +67,9 @@ typedef unsigned long int uintmax_t;
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#undef __HAVE_LONG_LONG__
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typedef uint8_t u8;
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typedef uint16_t u16;
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typedef uint32_t u32;
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#endif /* I386_STDINT_H */
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@ -356,7 +356,6 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
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return bsp_apicid;
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}
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#if CONFIG_LOGICAL_CPUS == 1
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static unsigned is_core0_started(unsigned nodeid)
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{
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@ -383,4 +382,3 @@ static void wait_all_core0_started(void)
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}
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#endif
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@ -20,8 +20,6 @@
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#include <string.h>
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#include <cpu/x86/msr.h>
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typedef unsigned int u32;
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/* The maximum length of CPU names is 48 bytes, including the final NULL byte.
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* If you change these names your BIOS will _NOT_ pass the AMD validation and
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* your mainboard will not be posted on the AMD Recommended Motherboard Website
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@ -19,11 +19,11 @@ gdtptr:
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/* selgdt 0x08, flat code segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x9b, 0xcf, 0x00
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.byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */
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/* selgdt 0x10,flat data segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x93, 0xcf, 0x00
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.byte 0x00, 0x93, 0xcf, 0x00
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gdt_end:
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@ -42,6 +42,7 @@ static void set_var_mtrr(
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{
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/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
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/* FIXME: It only support 4G less range */
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msr_t basem, maskm;
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basem.lo = base | type;
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basem.hi = 0;
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@ -282,10 +282,16 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc
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}
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#ifndef CONFIG_VAR_MTRR_HOLE
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#define CONFIG_VAR_MTRR_HOLE 1
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#endif
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struct var_mtrr_state {
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unsigned long range_startk, range_sizek;
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unsigned int reg;
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#if CONFIG_VAR_MTRR_HOLE
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unsigned long hole_startk, hole_sizek;
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#endif
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unsigned address_bits;
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};
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@ -308,6 +314,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
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}
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/* Write the range mtrrs */
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if (state->range_sizek != 0) {
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#if CONFIG_VAR_MTRR_HOLE
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if (state->hole_sizek == 0) {
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/* We need to put that on to hole */
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unsigned long endk = basek + sizek;
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@ -316,17 +323,22 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
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state->range_sizek = endk - state->range_startk;
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return;
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}
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#endif
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state->reg = range_to_mtrr(state->reg, state->range_startk,
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state->range_sizek, basek, MTRR_TYPE_WRBACK, state->address_bits);
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#if CONFIG_VAR_MTRR_HOLE
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state->reg = range_to_mtrr(state->reg, state->hole_startk,
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state->hole_sizek, basek, MTRR_TYPE_UNCACHEABLE, state->address_bits);
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#endif
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state->range_startk = 0;
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state->range_sizek = 0;
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#if CONFIG_VAR_MTRR_HOLE
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state->hole_startk = 0;
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state->hole_sizek = 0;
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#endif
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}
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/* Allocate an msr */
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printk_spew(" Allocate an msr - basek = %d, sizek = %d,\n", basek, sizek);
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printk_spew(" Allocate an msr - basek = %08x, sizek = %08x,\n", basek, sizek);
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state->range_startk = basek;
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state->range_sizek = sizek;
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}
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@ -377,8 +389,10 @@ void x86_setup_var_mtrrs(unsigned address_bits)
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*/
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var_state.range_startk = 0;
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var_state.range_sizek = 0;
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#if CONFIG_VAR_MTRR_HOLE
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var_state.hole_startk = 0;
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var_state.hole_sizek = 0;
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#endif
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var_state.reg = 0;
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var_state.address_bits = address_bits;
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search_global_resources(
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@ -388,8 +402,10 @@ void x86_setup_var_mtrrs(unsigned address_bits)
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/* Write the last range */
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var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk,
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var_state.range_sizek, 0, MTRR_TYPE_WRBACK, var_state.address_bits);
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#if CONFIG_VAR_MTRR_HOLE
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var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk,
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var_state.hole_sizek, 0, MTRR_TYPE_UNCACHEABLE, var_state.address_bits);
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#endif
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printk_debug("DONE variable MTRRs\n");
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printk_debug("Clear out the extra MTRR's\n");
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/* Clear out the extra MTRR's */
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