mb/google/dedede: Add mainboard acpi support for GPIO PM configuration

Setting the default values for GPIO community power management, causes
issues in detecting TPM interrupts. So to avoid that GPIO PM has to be
disabled in devicetree. But for S0ix it is needed. This patch implements
a workaround in ASL code to enable GPIO PM on S0ix entry and disable it
on S0ix exit.

This patch adds the following three platform specific methods.

1. MS0X to enable power management features for GPIO communities on
low power mode entry and disables it on exit.

2. MPTS to enable power management features for GPIO communities when
preparing to sleep.

3. MWAK to disable power management features for GPIO communities on
waking up.

BUG=b:153847814
TEST=Verify S0ix is working. GPIO PM configuration is upadated on low
     power mode entry and exit.

Change-Id: I7225b78ab2ac5bf17f93230cd85cd21e836d807d
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41502
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/dedede/acpi/mainboard.asl

@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <intelblocks/gpio.h>
+#include <soc/gpio_soc_defs.h>
+
+Method (PGPM, 1, Serialized)
+{
+	For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
+	{
+		\_SB.PCI0.CGPM (Local0, Arg0)
+	}
+}
+
+/*
+ * Method called from _PTS prior to system sleep state entry
+ * Enables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MPTS, 1, Serialized)
+{
+	PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+}
+
+/*
+ * Method called from _WAK prior to system sleep state wakeup
+ * Disables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MWAK, 1, Serialized)
+{
+	PGPM (0)
+}
+
+/*
+ * S0ix Entry/Exit Notifications
+ * Called from \_SB.LPID._DSM
+ */
+Method (MS0X, 1, Serialized)
+{
+	If (Arg0 == 1) {
+		/* S0ix Entry */
+		PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+	} Else {
+		/* S0ix Exit */
+		PGPM (0)
+	}
+}

src/mainboard/google/dedede/dsdt.asl

@@ -27,6 +27,9 @@ DefinitionBlock(
 			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 			#include <soc/intel/jasperlake/acpi/southbridge.asl>
 		}
+
+		/* Mainboard hooks */
+		#include "acpi/mainboard.asl"
 	}
 
 #if CONFIG(VARIANT_HAS_CAMERA_ACPI)
@@ -34,6 +37,11 @@ DefinitionBlock(
 	#include <variant/acpi/camera.asl>
 #endif
 
+
+	/* Include Low power idle table for a short term workaround to enable
+	   S0ix. Once cr50 pulse width is fixed, this can be removed. */
+	#include <soc/intel/common/acpi/lpit.asl>
+
 	/* Chrome OS specific */
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>