soc/intel/common/block: Add Intel common PMC controller support for KBL, APL
SoC needs to select specific macros to compile commom PMC code. TEST=Build and boot KBL (soraka/eve), APL (reef) Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik
parent
07f065a3ce
commit
2153ea5b83
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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* Copyright (C) 2016-2017 Intel Corp.
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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@ -15,74 +15,27 @@
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* GNU General Public License for more details.
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*/
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#include "chip.h"
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <intelblocks/pmc.h>
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#include <intelblocks/pmclib.h>
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#include <soc/iomap.h>
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#include <soc/gpio.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <timer.h>
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#include "chip.h"
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/*
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* The ACPI IO BAR (offset 0x20) is not PCI compliant. We've observed cases
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* where the BAR reads back as 0, but the IO window is open. This also means
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* that it will not respond to PCI probing. In the event that probing the BAR
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* fails, we still need to create a resource for it.
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*/
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static void read_resources(device_t dev)
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/* Fill up PMC resource structure */
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int pmc_soc_get_resources(struct pmc_resource_config *cfg)
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{
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struct resource *res;
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pci_dev_read_resources(dev);
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cfg->pwrmbase_offset = PCI_BASE_ADDRESS_0;
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cfg->pwrmbase_addr = PMC_BAR0;
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cfg->pwrmbase_size = PMC_BAR0_SIZE;
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cfg->abase_offset = PCI_BASE_ADDRESS_4;
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cfg->abase_addr = ACPI_BASE_ADDRESS;
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cfg->abase_size = ACPI_BASE_SIZE;
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res = new_resource(dev, PCI_BASE_ADDRESS_0);
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res->base = PMC_BAR0;
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res->size = PMC_BAR0_SIZE;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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res = new_resource(dev, PCI_BASE_ADDRESS_4);
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res->base = ACPI_BASE_ADDRESS;
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res->size = ACPI_BASE_SIZE;
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res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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}
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/*
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* Part 2:
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* Resources are assigned, and no other device was given an IO resource to
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* overlap with our ACPI BAR. But because the resource is FIXED,
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* pci_dev_set_resources() will not store it for us. We need to do that
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* explicitly.
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*/
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static void set_resources(device_t dev)
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{
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struct resource *res;
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pci_dev_set_resources(dev);
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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pci_write_config32(dev, res->index, res->base);
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dev->command |= PCI_COMMAND_MEMORY;
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res->flags |= IORESOURCE_STORED;
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report_resource_stored(dev, res, " PMC BAR");
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res = find_resource(dev, PCI_BASE_ADDRESS_4);
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pci_write_config32(dev, res->index, res->base);
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dev->command |= PCI_COMMAND_IO;
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res->flags |= IORESOURCE_STORED;
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report_resource_stored(dev, res, " ACPI BAR");
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}
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static void pch_set_acpi_mode(void)
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{
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if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
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printk(BIOS_DEBUG, "Disabling ACPI via APMC:");
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outb(APM_CNT_ACPI_DISABLE, APM_CNT);
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printk(BIOS_DEBUG, "Done.\n");
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}
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return 0;
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}
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static int choose_slp_s3_assertion_width(int width_usecs)
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@ -138,14 +91,14 @@ static void set_slp_s3_assertion_width(int width_usecs)
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write32((void *)gen_pmcon3, reg);
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}
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static void pmc_init(struct device *dev)
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void pmc_soc_init(struct device *dev)
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{
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const struct soc_intel_apollolake_config *cfg = dev->chip_info;
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/* Set up GPE configuration */
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pmc_gpe_init();
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pmc_fixup_power_state();
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pch_set_acpi_mode();
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pmc_set_acpi_mode();
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if (cfg != NULL)
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set_slp_s3_assertion_width(cfg->slp_s3_assertion_width_usecs);
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@ -156,22 +109,3 @@ static void pmc_init(struct device *dev)
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/* Now that things have been logged clear out the PMC state. */
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pmc_clear_prsts();
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}
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static const struct device_operations device_ops = {
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.read_resources = read_resources,
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.set_resources = set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = &pmc_init,
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_APL_PMC,
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PCI_DEVICE_ID_INTEL_GLK_PMC,
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0,
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};
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static const struct pci_driver pmc __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices= pci_device_ids,
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};
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@ -0,0 +1,67 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SOC_INTEL_COMMON_BLOCK_PMC_H
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#define SOC_INTEL_COMMON_BLOCK_PMC_H
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#include <device/device.h>
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#include <stdint.h>
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/* PMC controller resource structure */
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struct pmc_resource_config {
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/* PMC PCI config offset for MMIO BAR */
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uint8_t pwrmbase_offset;
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/* MMIO BAR address */
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uintptr_t pwrmbase_addr;
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/* MMIO BAR size */
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size_t pwrmbase_size;
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/* PMC PCI config offset for IO BAR */
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uint8_t abase_offset;
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/* IO BAR address */
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uintptr_t abase_addr;
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/* IO BAR size */
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size_t abase_size;
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};
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/*
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* SoC overrides
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*
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* All new SoCs wishes to make use of common PMC PCI driver
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* must implement below functionality .
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*/
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/*
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* Function to initialize PMC controller.
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*
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* This initialization may differ between different SoC
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*
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* Input: Device Structure PMC PCI device
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*/
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void pmc_soc_init(struct device *dev);
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/*
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* SoC should fill this structure information based on
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* PMC controller register information like PWRMBASE, ABASE offset
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* BAR and Size
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*
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* Input: PMC config structure
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* Output: -1 = Error, 0 = Success
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*/
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int pmc_soc_get_resources(struct pmc_resource_config *cfg);
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/* API to set ACPI mode */
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void pmc_set_acpi_mode(void);
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#endif /* SOC_INTEL_COMMON_BLOCK_PMC_H */
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@ -1,5 +1,8 @@
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bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c
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romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c
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smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c
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verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c
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ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC),y)
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bootblock-y += pmclib.c
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romstage-y += pmclib.c
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ramstage-y += pmc.c
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ramstage-y += pmclib.c
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smm-y += pmclib.c
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verstage-y += pmclib.c
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endif
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@ -0,0 +1,117 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <intelblocks/pmc.h>
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#include <soc/pci_devs.h>
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/* SoC overrides */
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/* Fill up PMC resource structure inside SoC directory */
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__attribute__((weak)) int pmc_soc_get_resources(
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struct pmc_resource_config *cfg)
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{
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/* no-op */
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return -1;
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}
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/* SoC override PMC initialization */
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__attribute__((weak)) void pmc_soc_init(struct device *dev)
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{
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/* no-op */
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}
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static void pch_pmc_add_new_resource(struct device *dev,
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uint8_t offset, uintptr_t base, size_t size,
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unsigned long flags)
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{
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struct resource *res;
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res = new_resource(dev, offset);
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res->base = base;
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res->size = size;
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res->flags = flags;
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}
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static void pch_pmc_add_mmio_resources(struct device *dev,
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const struct pmc_resource_config *cfg)
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{
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pch_pmc_add_new_resource(dev, cfg->pwrmbase_offset,
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cfg->pwrmbase_addr, cfg->pwrmbase_size,
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IORESOURCE_MEM | IORESOURCE_ASSIGNED |
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IORESOURCE_FIXED | IORESOURCE_RESERVE);
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}
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static void pch_pmc_add_io_resources(struct device *dev,
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const struct pmc_resource_config *cfg)
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{
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pch_pmc_add_new_resource(dev, cfg->abase_offset,
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cfg->abase_addr, cfg->abase_size,
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IORESOURCE_IO | IORESOURCE_ASSIGNED |
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IORESOURCE_FIXED);
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}
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static void pch_pmc_read_resources(struct device *dev)
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{
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struct pmc_resource_config pmc_cfg;
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struct pmc_resource_config *config = &pmc_cfg;
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if (pmc_soc_get_resources(config) < 0)
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die("Unable to get PMC controller resource information!");
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/* Get the normal PCI resources of this device. */
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pci_dev_read_resources(dev);
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/* Add non-standard MMIO resources. */
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pch_pmc_add_mmio_resources(dev, config);
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/* Add IO resources. */
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pch_pmc_add_io_resources(dev, config);
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}
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void pmc_set_acpi_mode(void)
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{
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if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
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printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
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outb(APM_CNT_ACPI_DISABLE, APM_CNT);
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printk(BIOS_DEBUG, "done.\n");
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}
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}
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static struct device_operations device_ops = {
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.read_resources = &pch_pmc_read_resources,
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.set_resources = &pci_dev_set_resources,
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.enable_resources = &pci_dev_enable_resources,
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.init = &pmc_soc_init,
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.scan_bus = &scan_lpc_bus,
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_SPT_LP_PMC,
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PCI_DEVICE_ID_INTEL_KBP_H_PMC,
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PCI_DEVICE_ID_INTEL_APL_PMC,
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PCI_DEVICE_ID_INTEL_GLK_PMC,
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0
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};
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static const struct pci_driver pch_lpc __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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@ -37,6 +37,7 @@ romstage-y += memmap.c
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romstage-y += me.c
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romstage-y += pch.c
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romstage-y += pei_data.c
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romstage-y += pmc.c
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romstage-y += pmutil.c
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romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
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romstage-y += spi.c
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@ -3,7 +3,7 @@
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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* Copyright (C) 2015-2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -18,25 +18,40 @@
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#include <chip.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include <arch/ioapic.h>
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#include <arch/acpi.h>
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#include <cpu/cpu.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/pmc.h>
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#include <intelblocks/pmclib.h>
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#include <pc80/mc146818rtc.h>
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#include <intelblocks/rtc.h>
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#include <reg_script.h>
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#include <string.h>
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#include <soc/gpio.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/pmc.h>
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#include <cpu/x86/smm.h>
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#include <soc/pcr_ids.h>
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#include <soc/ramstage.h>
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void pmc_set_disb(void)
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{
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/* Set the DISB after DRAM init */
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u32 disb_val;
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device_t dev = PCH_DEV_PMC;
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disb_val = pci_read_config32(dev, GEN_PMCON_A);
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disb_val |= DISB;
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/* Don't clear bits that are write-1-to-clear */
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disb_val &= ~(GBL_RST_STS | MS4V);
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pci_write_config32(dev, GEN_PMCON_A, disb_val);
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}
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#if ENV_RAMSTAGE
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/* Fill up PMC resource structure */
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int pmc_soc_get_resources(struct pmc_resource_config *cfg)
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{
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cfg->pwrmbase_offset = PWRMBASE;
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cfg->pwrmbase_addr = PCH_PWRM_BASE_ADDRESS;
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cfg->pwrmbase_size = PCH_PWRM_BASE_SIZE;
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cfg->abase_offset = ABASE;
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cfg->abase_addr = ACPI_BASE_ADDRESS;
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cfg->abase_size = ACPI_BASE_SIZE;
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return 0;
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}
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static const struct reg_script pch_pmc_misc_init_script[] = {
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/* SLP_S4=4s, SLP_S3=50ms, disable SLP_X stretching after SUS loss. */
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@ -58,68 +73,11 @@ static const struct reg_script pmc_write1_to_clear_script[] = {
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REG_SCRIPT_END
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};
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static void pch_pmc_add_mmio_resources(device_t dev)
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{
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struct resource *res;
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/* Memory-mmapped I/O registers. */
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res = new_resource(dev, PWRMBASE);
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res->base = PCH_PWRM_BASE_ADDRESS;
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res->size = PCH_PWRM_BASE_SIZE;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
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IORESOURCE_FIXED | IORESOURCE_RESERVE;
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}
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static void pch_pmc_add_io_resource(device_t dev, u16 base, u16 size, int index)
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{
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struct resource *res;
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res = new_resource(dev, index);
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res->base = base;
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res->size = size;
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res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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}
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static void pch_pmc_add_io_resources(device_t dev)
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{
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/* PMBASE */
|
||||
pch_pmc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE);
|
||||
}
|
||||
|
||||
static void pch_pmc_read_resources(device_t dev)
|
||||
{
|
||||
/* Get the normal PCI resources of this device. */
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
/* Add non-standard MMIO resources. */
|
||||
pch_pmc_add_mmio_resources(dev);
|
||||
|
||||
/* Add IO resources. */
|
||||
pch_pmc_add_io_resources(dev);
|
||||
}
|
||||
|
||||
static void pch_set_acpi_mode(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
|
||||
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
|
||||
outb(APM_CNT_ACPI_DISABLE, APM_CNT);
|
||||
printk(BIOS_DEBUG, "done.\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void pch_rtc_init(void)
|
||||
{
|
||||
/* Ensure the date is set including century byte. */
|
||||
cmos_check_update_date();
|
||||
|
||||
cmos_init(rtc_failure());
|
||||
}
|
||||
|
||||
static void pch_power_options(void)
|
||||
static void pch_power_options(struct device *dev)
|
||||
{
|
||||
u16 reg16;
|
||||
const char *state;
|
||||
/*PMC Controller Device 0x1F, Func 02*/
|
||||
device_t dev = PCH_DEV_PMC;
|
||||
|
||||
/* Get the chip configuration */
|
||||
int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
|
||||
|
||||
|
|
@ -199,19 +157,19 @@ static void config_deep_sx(uint32_t deepsx_config)
|
|||
write32(pmcbase + DSX_CFG, reg);
|
||||
}
|
||||
|
||||
static void pmc_init(struct device *dev)
|
||||
void pmc_soc_init(struct device *dev)
|
||||
{
|
||||
config_t *config = dev->chip_info;
|
||||
const config_t *config = dev->chip_info;
|
||||
|
||||
pch_rtc_init();
|
||||
rtc_init();
|
||||
|
||||
/* Initialize power management */
|
||||
pch_power_options();
|
||||
pch_power_options(dev);
|
||||
|
||||
/* Note that certain bits may be cleared from running script as
|
||||
* certain bit fields are write 1 to clear. */
|
||||
reg_script_run_on_dev(dev, pch_pmc_misc_init_script);
|
||||
pch_set_acpi_mode();
|
||||
pmc_set_acpi_mode();
|
||||
|
||||
config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
|
||||
config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
|
||||
|
|
@ -220,24 +178,4 @@ static void pmc_init(struct device *dev)
|
|||
/* Clear registers that contain write-1-to-clear bits. */
|
||||
reg_script_run_on_dev(dev, pmc_write1_to_clear_script);
|
||||
}
|
||||
|
||||
static struct device_operations device_ops = {
|
||||
.read_resources = &pch_pmc_read_resources,
|
||||
.set_resources = &pci_dev_set_resources,
|
||||
.enable_resources = &pci_dev_enable_resources,
|
||||
.init = &pmc_init,
|
||||
.scan_bus = &scan_lpc_bus,
|
||||
.ops_pci = &soc_pci_ops,
|
||||
};
|
||||
|
||||
static const unsigned short pci_device_ids[] = {
|
||||
0x9d21,
|
||||
0xa121,
|
||||
0
|
||||
};
|
||||
|
||||
static const struct pci_driver pch_lpc __pci_driver = {
|
||||
.ops = &device_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.devices = pci_device_ids,
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,5 +1,4 @@
|
|||
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += car_stage.S
|
||||
romstage-y += pmc.c
|
||||
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c
|
||||
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c
|
||||
romstage-y += systemagent.c
|
||||
|
|
|
|||
|
|
@ -1,30 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2016 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/pm.h>
|
||||
|
||||
void pmc_set_disb(void)
|
||||
{
|
||||
/* Set the DISB after DRAM init */
|
||||
u32 disb_val = 0;
|
||||
pci_devfn_t dev = PCH_DEV_PMC;
|
||||
disb_val = pci_read_config32(dev, GEN_PMCON_A);
|
||||
disb_val |= DISB;
|
||||
|
||||
/* Don't clear bits that are write-1-to-clear */
|
||||
disb_val &= ~(GBL_RST_STS | MS4V);
|
||||
pci_write_config32(dev, GEN_PMCON_A, disb_val);
|
||||
}
|
||||
Loading…
Reference in New Issue