From 21573e9f4e6c5ec1c5ab7da265f42642f832394b Mon Sep 17 00:00:00 2001
From: Lijian Zhao <lijian.zhao@intel.com>
Date: Wed, 8 Nov 2017 19:21:32 -0800
Subject: [PATCH] soc/intel/cannonlake: Add ACPI workaround for EMMC

Two W/A had been added here for EMMC to make it working properly.
1. Enable power gating after D3 entry, disable power gating before D0
entry.
2. Add 50 ms delay to ensure Rcomp calibration done before EMMC out of
D3.

BUG=b:69323943
TEST=Run multiple ACPI S3 cycles on cannonlake u LPDDR4 platform.

Change-Id: Ic6e98264521fb02b911a8c157a7982afa35fe20c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/cannonlake/acpi/scs.asl | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl
index 11564ae7d4..ed695fd580 100644
--- a/src/soc/intel/cannonlake/acpi/scs.asl
+++ b/src/soc/intel/cannonlake/acpi/scs.asl
@@ -14,6 +14,26 @@
  */
 
 Scope (\_SB.PCI0) {
+	/* EMMC */
+	Device(PEMC) {
+		Name(_ADR, 0x001A0000)
+
+		OperationRegion(SCSR, PCI_Config, 0x00, 0x100)
+		Field(SCSR, WordAcc, NoLock, Preserve) {
+			Offset(0xA2),   // 0xA2, Device PG config
+			, 2,
+			PGEN, 1         // [BIT2] PGE - PG Enable
+		}
+
+		Method(_PS0, 0, Serialized) {
+			Stall (50) // Sleep 50 ms
+			Store(0, PGEN) // Disable PG
+		}
+
+		Method(_PS3, 0, Serialized) {
+			Store(1, PGEN) // Enable PG
+		}
+	}
 
 	/* SD CARD */
 	Device (SDXC)