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drivers/intel/fsp1_1: Fix issues detected by checkpatch 

Fix the following error and warnings detected by checkpatch.pl:

ERROR: "foo * bar" should be "foo *bar"
WARNING: line over 80 characters
WARNING: else is not generally useful after a break or return
WARNING: braces {} are not necessary for single statement blocks
WARNING: suspect code indent for conditional statements (16, 32)
WARNING: Comparisons should place the constant on the right side of the test

TEST=Build and run on Galileo Gen2

Change-Id: I9f56c0b0e3baf84989411e4a4b98f935725c013f
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18886
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
This commit is contained in:
Lee Leahy 2017-03-17 11:23:32 -07:00
parent 6ef5192627
commit 216712ae01
7 changed files with 27 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/drivers/intel/fsp1_1/fsp_gop.c
View File

@ -71,10 +71,9 @@ void lb_framebuffer(struct lb_header *header)
if (vbt_hob == NULL) {
printk(BIOS_ERR, "FSP_ERR: Graphics Data HOB is not present\n");
return;
} else {
}
printk(BIOS_DEBUG, "FSP_DEBUG: Graphics Data HOB present\n");
vbt_gop = GET_GUID_HOB_DATA(vbt_hob);
}
framebuffer->physical_address = vbt_gop->FrameBufferBase;
framebuffer->x_resolution = vbt_gop->GraphicsMode.HorizontalResolution;

15
src/drivers/intel/fsp1_1/fsp_util.c
View File

@ -45,9 +45,8 @@ FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address)
fsp_ptr.u32 = fsp_base_address;
/* Check the FV signature, _FVH */
if (fsp_ptr.fvh->Signature != 0x4856465F) {
if (fsp_ptr.fvh->Signature != 0x4856465F)
return (FSP_INFO_HEADER *)ERROR_NO_FV_SIG;
}
/* Locate the file header which follows the FV header. */
fsp_ptr.u32 += fsp_ptr.fvh->ExtHeaderOffset;
@ -65,22 +64,19 @@ FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address)
/* Locate the Raw Section Header */
fsp_ptr.u32 += sizeof(EFI_FFS_FILE_HEADER);
if (fsp_ptr.rs->Type != EFI_SECTION_RAW) {
if (fsp_ptr.rs->Type != EFI_SECTION_RAW)
return (FSP_INFO_HEADER *)ERROR_NO_INFO_HEADER;
}
/* Locate the FSP INFO Header which follows the Raw Header. */
fsp_ptr.u32 += sizeof(EFI_RAW_SECTION);
/* Verify that the FSP base address.*/
if (fsp_ptr.fih->ImageBase != fsp_base_address) {
if (fsp_ptr.fih->ImageBase != fsp_base_address)
return (FSP_INFO_HEADER *)ERROR_IMAGEBASE_MISMATCH;
}
/* Verify the FSP Signature */
if (fsp_ptr.fih->Signature != FSP_SIG) {
if (fsp_ptr.fih->Signature != FSP_SIG)
return (FSP_INFO_HEADER *)ERROR_INFO_HEAD_SIG_MISMATCH;
}
/* Verify the FSP ID */
image_id = (u32 *)&fsp_ptr.fih->ImageId[0];
@ -290,7 +286,8 @@ void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old,
}
}
size_t EFIAPI fsp_write_line(uint8_t *buffer, size_t number_of_bytes)
__attribute__((cdecl)) size_t fsp_write_line(uint8_t *buffer,
size_t number_of_bytes)
{
console_write_line(buffer, number_of_bytes);
return number_of_bytes;

2
src/drivers/intel/fsp1_1/hob.c
View File

@ -69,7 +69,7 @@ void *get_first_hob(uint16_t type)
}
/* Returns the next instance of the matched GUID HOB from the starting HOB. */
void *get_next_guid_hob(const EFI_GUID * guid, const void *hob_start)
void *get_next_guid_hob(const EFI_GUID *guid, const void *hob_start)
{
EFI_PEI_HOB_POINTERS hob;

14
src/drivers/intel/fsp1_1/include/fsp/util.h
View File

@ -92,12 +92,11 @@ int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src);
extern void *FspHobListPtr;
#endif
/* TODO: Remove the EFI types and decorations from coreboot implementations. */
VOID * EFIAPI get_hob_list(VOID);
VOID * EFIAPI get_next_hob(UINT16 type, CONST VOID *hob_start);
VOID * EFIAPI get_first_hob(UINT16 type);
VOID * EFIAPI get_next_guid_hob(CONST EFI_GUID * guid, CONST VOID *hob_start);
VOID * EFIAPI get_first_guid_hob(CONST EFI_GUID * guid);
void *get_hob_list(void);
void *get_next_hob(uint16_t type, const void *hob_start);
void *get_first_hob(uint16_t type);
void *get_next_guid_hob(const EFI_GUID *guid, const void *hob_start);
void *get_first_guid_hob(const EFI_GUID *guid);
/*
* Writes number_of_bytes data bytes from buffer to the console.
@ -106,6 +105,7 @@ VOID * EFIAPI get_first_guid_hob(CONST EFI_GUID * guid);
* If number_of_bytes is zero, don't output any data but instead wait until
* the console has output all data, then return 0.
*/
size_t EFIAPI fsp_write_line(uint8_t *buffer, size_t number_of_bytes);
__attribute__((cdecl)) size_t fsp_write_line(uint8_t *buffer,
size_t number_of_bytes);
#endif /* FSP1_1_UTIL_H */

6
src/drivers/intel/fsp1_1/raminit.c
View File

@ -183,7 +183,7 @@ void raminit(struct romstage_params *params)
/* Locate the FSP_SMBIOS_MEMORY_INFO HOB */
memory_info_hob = get_next_guid_hob(&memory_info_hob_guid,
hob_list_ptr);
if (NULL == memory_info_hob) {
if (memory_info_hob == NULL) {
printk(BIOS_ERR, "FSP_SMBIOS_MEMORY_INFO HOB missing!\n");
fsp_verification_failure = 1;
} else {
@ -205,7 +205,7 @@ void raminit(struct romstage_params *params)
* 7.5: EFI_PEI_GRAPHICS_INFO_HOB produced by SiliconInit
* FSP_SMBIOS_MEMORY_INFO HOB verified above
*/
if (NULL != cbmem_root) {
if (cbmem_root != NULL) {
printk(BIOS_DEBUG,
"7.4: FSP_BOOTLOADER_TOLUM_HOB: 0x%p\n",
cbmem_root);
@ -215,7 +215,7 @@ void raminit(struct romstage_params *params)
printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data);
}
hob_ptr.Raw = get_next_guid_hob(&mrc_guid, hob_list_ptr);
if (NULL == hob_ptr.Raw) {
if (hob_ptr.Raw == NULL) {
printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n");
fsp_verification_failure =
(params->pei_data->saved_data == NULL) ? 1 : 0;

6
src/drivers/intel/fsp1_1/stack.c
View File

@ -71,7 +71,8 @@ void *setup_stack_and_mtrrs(void)
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
slot = stack_push32(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
slot = stack_push32(slot, ~(CACHE_TMP_RAMTOP - 1)
| MTRR_PHYS_MASK_VALID);
slot = stack_push32(slot, 0); /* upper base */
slot = stack_push32(slot, 0 | MTRR_TYPE_WRBACK);
num_mtrrs++;
@ -136,7 +137,8 @@ void *setup_stack_and_mtrrs(void)
/* Cache the ROM as WP just below 4GiB. */
slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);
slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1)
| MTRR_PHYS_MASK_VALID);
slot = stack_push32(slot, 0); /* upper base */
slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
num_mtrrs++;