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Rambi: Enable 32k SUSCLK signal 

The SoC needs to provide a 32k clock signal SUSCLK for
some modems to work properly, so this enables the signal.

BUG=chrome-os-partner:24425
TEST=Manual, check SUSCLK pin with a scope.

Change-Id: Ibc0d5bb38a2c3e16f381dfc256097fdced67fd1c
Reviewed-on: https://chromium-review.googlesource.com/180101
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Bernie Thompson <bhthompson@chromium.org>
Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5722
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Kyösti Mälkki 2014-05-12 23:16:18 +03:00
parent 6a70258c69
commit 216a619a74
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/rambi/gpio.c
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@ -168,7 +168,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = {
GPIO_FUNC6, /* S502 - TOUCH_INT# - INT */
GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */
GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */
GPIO_NC, /* S505 - SUS_CLK_WLAN (NC) */
GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */
GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */
GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */
GPIO_NC, /* S508 - NC */