diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index 876ec51169..dc532682d9 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -45,6 +45,23 @@ config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR
 	  Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented)
 	  to make `HECI1` device disable using private configuration register (PCR) write.
 
+config SOC_INTEL_STORE_CSE_FW_VERSION
+	bool
+	default n
+	depends on SOC_INTEL_CSE_LITE_SKU
+	help
+	  This configuration option stores CSE RW FW version in CBMEM area.
+	  This information can be used to identify if the CSE firmware update is successful
+	  by comparing the currently running CSE RW firmware version against CSE version
+	  belongs to the CONFIG_SOC_INTEL_CSE_RW_VERSION (decided statically while
+	  building the AP FW image).
+
+	  The way to retrieve the CSE firmware version is by sending the HECI command to
+	  read the CSE Boot Partition (BP) info. The cost of sending HECI command to read
+	  the CSE FW version is between 7ms-20ms (depending on the SoC architecture) hence,
+	  ensure this feature is platform specific and only enabled for the platform
+	  that would like to store the CSE version into the CBMEM.
+
 config SOC_INTEL_STORE_ISH_FW_VERSION
 	bool
 	default n
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index ea956a70f1..14637cedc4 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -1438,7 +1438,7 @@ static void intel_cse_get_rw_version(void)
  */
 static void cse_final(struct device *dev)
 {
-	if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
+	if (CONFIG(SOC_INTEL_STORE_CSE_FW_VERSION))
 		intel_cse_get_rw_version();
 	/*
 	 * SoC user can have two options for sending EOP:
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index dd3f173313..d3fcec7ba4 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -1304,7 +1304,8 @@ static void ramstage_cse_misc_ops(void *unused)
 		cse_fw_sync();
 
 	/* Store the CSE RW Firmware Version into CBMEM */
-	cse_store_rw_fw_version();
+	if (CONFIG(SOC_INTEL_STORE_CSE_FW_VERSION))
+		cse_store_rw_fw_version();
 	/*
 	 * Store the ISH RW Firmware Version into CBMEM if ISH partition
 	 * is available