sb/intel/lynxpoint: Move IOBP API to its own compilation unit

Change-Id: Icb6114302cebe19bc3c1971929ea4fc085b454be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41946
Reviewed-by: Michael Niewöhner
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jonathan Kollasch <jakllsch@kollasch.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/southbridge/intel/lynxpoint/Makefile.inc

@@ -5,6 +5,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y)
 bootblock-y += bootblock.c
 
 ramstage-y += pch.c
+ramstage-y += iobp.c
 ramstage-y += azalia.c
 ramstage-y += fadt.c
 ramstage-y += lpc.c

src/southbridge/intel/lynxpoint/iobp.c

@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <delay.h>
+#include "pch.h"
+#include "iobp.h"
+
+#define IOBP_RETRY 1000
+
+static inline int iobp_poll(void)
+{
+	unsigned int try;
+
+	for (try = IOBP_RETRY; try > 0; try--) {
+		u16 status = RCBA16(IOBPS);
+		if ((status & IOBPS_READY) == 0)
+			return 1;
+		udelay(10);
+	}
+
+	printk(BIOS_ERR, "IOBP: timeout waiting for transaction to complete\n");
+	return 0;
+}
+
+u32 pch_iobp_read(u32 address)
+{
+	u16 status;
+
+	if (!iobp_poll())
+		return 0;
+
+	/* Set the address */
+	RCBA32(IOBPIRI) = address;
+
+	/* READ OPCODE */
+	status = RCBA16(IOBPS);
+	status &= ~IOBPS_MASK;
+	status |= IOBPS_READ;
+	RCBA16(IOBPS) = status;
+
+	/* Undocumented magic */
+	RCBA16(IOBPU) = IOBPU_MAGIC;
+
+	/* Set ready bit */
+	status = RCBA16(IOBPS);
+	status |= IOBPS_READY;
+	RCBA16(IOBPS) = status;
+
+	if (!iobp_poll())
+		return 0;
+
+	/* Check for successful transaction */
+	status = RCBA16(IOBPS);
+	if (status & IOBPS_TX_MASK) {
+		printk(BIOS_ERR, "IOBP: read 0x%08x failed\n", address);
+		return 0;
+	}
+
+	/* Read IOBP data */
+	return RCBA32(IOBPD);
+}
+
+void pch_iobp_write(u32 address, u32 data)
+{
+	u16 status;
+
+	if (!iobp_poll())
+		return;
+
+	/* Set the address */
+	RCBA32(IOBPIRI) = address;
+
+	/* WRITE OPCODE */
+	status = RCBA16(IOBPS);
+	status &= ~IOBPS_MASK;
+	status |= IOBPS_WRITE;
+	RCBA16(IOBPS) = status;
+
+	RCBA32(IOBPD) = data;
+
+	/* Undocumented magic */
+	RCBA16(IOBPU) = IOBPU_MAGIC;
+
+	/* Set ready bit */
+	status = RCBA16(IOBPS);
+	status |= IOBPS_READY;
+	RCBA16(IOBPS) = status;
+
+	if (!iobp_poll())
+		return;
+
+	/* Check for successful transaction */
+	status = RCBA16(IOBPS);
+	if (status & IOBPS_TX_MASK) {
+		printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address);
+		return;
+	}
+
+	printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data);
+}
+
+void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
+{
+	u32 data = pch_iobp_read(address);
+
+	/* Update the data */
+	data &= andvalue;
+	data |= orvalue;
+
+	pch_iobp_write(address, data);
+}

src/southbridge/intel/lynxpoint/iobp.h

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_IOBP_H
+#define SOUTHBRIDGE_INTEL_LYNXPOINT_IOBP_H
+
+#include <stdint.h>
+
+u32 pch_iobp_read(u32 address);
+void pch_iobp_write(u32 address, u32 data);
+void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
+
+#endif

src/southbridge/intel/lynxpoint/lpc.c

@@ -16,6 +16,7 @@
 #include <cbmem.h>
 #include <string.h>
 #include "chip.h"
+#include "iobp.h"
 #include "nvs.h"
 #include "pch.h"
 #include <acpi/acpigen.h>

src/southbridge/intel/lynxpoint/pch.c

@@ -6,6 +6,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_def.h>
+#include "iobp.h"
 #include "pch.h"
 
 #ifdef __SIMPLE_DEVICE__
@@ -183,110 +184,6 @@ void pch_disable_devfn(struct device *dev)
 	}
 }
 
-#define IOBP_RETRY 1000
-static inline int iobp_poll(void)
-{
-	unsigned int try;
-
-	for (try = IOBP_RETRY; try > 0; try--) {
-		u16 status = RCBA16(IOBPS);
-		if ((status & IOBPS_READY) == 0)
-			return 1;
-		udelay(10);
-	}
-
-	printk(BIOS_ERR, "IOBP: timeout waiting for transaction to complete\n");
-	return 0;
-}
-
-u32 pch_iobp_read(u32 address)
-{
-	u16 status;
-
-	if (!iobp_poll())
-		return 0;
-
-	/* Set the address */
-	RCBA32(IOBPIRI) = address;
-
-	/* READ OPCODE */
-	status = RCBA16(IOBPS);
-	status &= ~IOBPS_MASK;
-	status |= IOBPS_READ;
-	RCBA16(IOBPS) = status;
-
-	/* Undocumented magic */
-	RCBA16(IOBPU) = IOBPU_MAGIC;
-
-	/* Set ready bit */
-	status = RCBA16(IOBPS);
-	status |= IOBPS_READY;
-	RCBA16(IOBPS) = status;
-
-	if (!iobp_poll())
-		return 0;
-
-	/* Check for successful transaction */
-	status = RCBA16(IOBPS);
-	if (status & IOBPS_TX_MASK) {
-		printk(BIOS_ERR, "IOBP: read 0x%08x failed\n", address);
-		return 0;
-	}
-
-	/* Read IOBP data */
-	return RCBA32(IOBPD);
-}
-
-void pch_iobp_write(u32 address, u32 data)
-{
-	u16 status;
-
-	if (!iobp_poll())
-		return;
-
-	/* Set the address */
-	RCBA32(IOBPIRI) = address;
-
-	/* WRITE OPCODE */
-	status = RCBA16(IOBPS);
-	status &= ~IOBPS_MASK;
-	status |= IOBPS_WRITE;
-	RCBA16(IOBPS) = status;
-
-	RCBA32(IOBPD) = data;
-
-	/* Undocumented magic */
-	RCBA16(IOBPU) = IOBPU_MAGIC;
-
-	/* Set ready bit */
-	status = RCBA16(IOBPS);
-	status |= IOBPS_READY;
-	RCBA16(IOBPS) = status;
-
-	if (!iobp_poll())
-		return;
-
-	/* Check for successful transaction */
-	status = RCBA16(IOBPS);
-	if (status & IOBPS_TX_MASK) {
-		printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address);
-		return;
-	}
-
-	printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data);
-}
-
-void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
-{
-	u32 data = pch_iobp_read(address);
-
-	/* Update the data */
-	data &= andvalue;
-	data |= orvalue;
-
-	pch_iobp_write(address, data);
-}
-
 void pch_enable(struct device *dev)
 {
 	/* PCH PCIe Root Ports are handled in PCIe driver. */

src/southbridge/intel/lynxpoint/pch.h

@@ -115,9 +115,6 @@ void disable_gpe(u32 mask);
 
 void pch_enable(struct device *dev);
 void pch_disable_devfn(struct device *dev);
-u32 pch_iobp_read(u32 address);
-void pch_iobp_write(u32 address, u32 data);
-void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
 void pch_log_state(void);
 void acpi_create_intel_hpet(acpi_hpet_t * hpet);
 void acpi_create_serialio_ssdt(acpi_header_t *ssdt);

src/southbridge/intel/lynxpoint/pcie.c

@@ -9,6 +9,7 @@
 #include <device/pciexp.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
+#include "iobp.h"
 #include "pch.h"
 #include <southbridge/intel/common/gpio.h>
 #include <stddef.h>

src/southbridge/intel/lynxpoint/sata.c

@@ -8,6 +8,7 @@
 #include <device/pci_ids.h>
 #include <delay.h>
 #include "chip.h"
+#include "iobp.h"
 #include "pch.h"
 
 typedef struct southbridge_intel_lynxpoint_config config_t;

src/southbridge/intel/lynxpoint/serialio.c

@@ -8,6 +8,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include "chip.h"
+#include "iobp.h"
 #include "pch.h"
 #include "nvs.h"
 

src/southbridge/intel/lynxpoint/usb_ehci.c

@@ -8,6 +8,7 @@
 #include <device/pci_ehci.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>
+#include "iobp.h"
 #include "pch.h"
 
 #ifdef __SIMPLE_DEVICE__

src/southbridge/intel/lynxpoint/usb_xhci.c

@@ -8,6 +8,7 @@
 #include <device/mmio.h>
 #include <device/pci_ops.h>
 #include "chip.h"
+#include "iobp.h"
 #include "pch.h"
 
 typedef struct southbridge_intel_lynxpoint_config config_t;