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soc/amd/common/block/gpio_banks/gpio: factor out set_gpio_mux 

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I75f1e45ead4a5f04cba1eecb220ef027a8bfd09e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56678
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2021-07-28 20:30:17 +02:00
parent e8fd7a42e0
commit 21813c3577
1 changed files with 7 additions and 2 deletions
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9
src/soc/amd/common/block/gpio_banks/gpio.c
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@ -160,6 +160,12 @@ uint16_t gpio_acpi_pin(gpio_t gpio)
return gpio;
}
static void set_gpio_mux(gpio_t gpio, uint8_t function)
{
iomux_write8(gpio, function & AMD_GPIO_MUX_MASK);
iomux_read8(gpio); /* Flush posted write */
}
static void set_single_gpio(const struct soc_amd_gpio *g)
{
static const struct soc_amd_event *gev_tbl;
@ -168,8 +174,7 @@ static void set_single_gpio(const struct soc_amd_gpio *g)
const bool can_set_smi_flags = !(CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) &&
ENV_SEPARATE_VERSTAGE);
iomux_write8(g->gpio, g->function & AMD_GPIO_MUX_MASK);
iomux_read8(g->gpio); /* Flush posted write */
set_gpio_mux(g->gpio, g->function);
gpio_setbits32(g->gpio, PAD_CFG_MASK, g->control);
/* Clear interrupt and wake status (write 1-to-clear bits) */