soc/amd/common/block/gpio_banks/gpio: factor out set_gpio_mux
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I75f1e45ead4a5f04cba1eecb220ef027a8bfd09e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56678 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -160,6 +160,12 @@ uint16_t gpio_acpi_pin(gpio_t gpio)
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return gpio;
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return gpio;
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}
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}
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static void set_gpio_mux(gpio_t gpio, uint8_t function)
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{
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iomux_write8(gpio, function & AMD_GPIO_MUX_MASK);
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iomux_read8(gpio); /* Flush posted write */
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}
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static void set_single_gpio(const struct soc_amd_gpio *g)
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static void set_single_gpio(const struct soc_amd_gpio *g)
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{
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{
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static const struct soc_amd_event *gev_tbl;
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static const struct soc_amd_event *gev_tbl;
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@ -168,8 +174,7 @@ static void set_single_gpio(const struct soc_amd_gpio *g)
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const bool can_set_smi_flags = !(CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) &&
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const bool can_set_smi_flags = !(CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) &&
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ENV_SEPARATE_VERSTAGE);
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ENV_SEPARATE_VERSTAGE);
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iomux_write8(g->gpio, g->function & AMD_GPIO_MUX_MASK);
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set_gpio_mux(g->gpio, g->function);
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iomux_read8(g->gpio); /* Flush posted write */
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gpio_setbits32(g->gpio, PAD_CFG_MASK, g->control);
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gpio_setbits32(g->gpio, PAD_CFG_MASK, g->control);
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/* Clear interrupt and wake status (write 1-to-clear bits) */
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/* Clear interrupt and wake status (write 1-to-clear bits) */
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