mb/siemens/chili/base: Add SMBIOS slot descriptions
Add SMBIOS slot descriptions for M.2 ports and remove duplicate comments. Change-Id: Ieff03ad3167aec054cdc6b67ddc20fc64394e347 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -86,8 +86,9 @@ chip soc/intel/cannonlake
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register "PcieRpSlotImplemented[5]" = "0"
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register "PcieRpSlotImplemented[5]" = "0"
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end
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end
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device pci 1c.6 on # PCI Express Port 7
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device pci 1c.6 on # PCI Express Port 7
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register "PcieRpEnable[6]" = "1" # x1 M.2 (WLAN / BT)
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register "PcieRpEnable[6]" = "1"
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register "PcieRpSlotImplemented[6]" = "1"
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register "PcieRpSlotImplemented[6]" = "1"
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smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
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end
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end
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 off end # PCI Express Port 9
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device pci 1d.0 off end # PCI Express Port 9
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@ -99,10 +100,11 @@ chip soc/intel/cannonlake
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device pci 1d.6 off end # PCI Express Port 15
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device pci 1d.6 off end # PCI Express Port 15
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device pci 1d.7 off end # PCI Express Port 16
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device pci 1d.7 off end # PCI Express Port 16
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device pci 1b.0 on # PCI Express Port 17
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device pci 1b.0 on # PCI Express Port 17
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register "PcieRpEnable[16]" = "1" # x4 M.2/M
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register "PcieRpEnable[16]" = "1"
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register "PcieClkSrcUsage[7]" = "16"
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register "PcieClkSrcUsage[7]" = "16"
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register "PcieClkSrcClkReq[7]" = "7"
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register "PcieClkSrcClkReq[7]" = "7"
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register "PcieRpSlotImplemented[16]" = "1"
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register "PcieRpSlotImplemented[16]" = "1"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
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end
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end
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device pci 1b.1 off end # PCI Express Port 18
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device pci 1b.1 off end # PCI Express Port 18
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device pci 1b.2 off end # PCI Express Port 19
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device pci 1b.2 off end # PCI Express Port 19
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