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amd/mct/ddr3: Fix incorrect DQ mask calculation 

On AMD DDR3 platforms, the upper DQMask was incorrectly
calculated, leading to undefined behaviour and possible
DRAM training faults.  Use the correct calculation for
the upper DQMask.

Found-by: Coverity Scan #1347394 #1347393
Change-Id: If3190eb7c30f1f00d6fd8b751bc1761c9d119782
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18068
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Timothy Pearson 2017-01-09 12:13:52 -06:00
parent ccc042b821
commit 21b01b80d6
1 changed files with 2 additions and 2 deletions
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4
src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
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@ -1073,7 +1073,7 @@ void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat,
Set_NB32_DCT(dev, dct, 0x27c, dword); Set_NB32_DCT(dev, dct, 0x27c, dword);
} else if (lane < 8) { } else if (lane < 8) {
Set_NB32_DCT(dev, dct, 0x274, ~0x0); Set_NB32_DCT(dev, dct, 0x274, ~0x0);
Set_NB32_DCT(dev, dct, 0x278, ~(0xff << (lane * 8))); Set_NB32_DCT(dev, dct, 0x278, ~(0xff << ((lane - 4) * 8)));
dword = Get_NB32_DCT(dev, dct, 0x27c); dword = Get_NB32_DCT(dev, dct, 0x27c);
dword |= 0xff; /* EccMask = 0xff */ dword |= 0xff; /* EccMask = 0xff */
Set_NB32_DCT(dev, dct, 0x27c, dword); Set_NB32_DCT(dev, dct, 0x27c, dword);
@ -1170,7 +1170,7 @@ void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat,
Set_NB32_DCT(dev, dct, 0x27c, dword); Set_NB32_DCT(dev, dct, 0x27c, dword);
} else if (lane < 8) { } else if (lane < 8) {
Set_NB32_DCT(dev, dct, 0x274, ~0x0); Set_NB32_DCT(dev, dct, 0x274, ~0x0);
Set_NB32_DCT(dev, dct, 0x278, ~(0xff << (lane * 8))); Set_NB32_DCT(dev, dct, 0x278, ~(0xff << ((lane - 4) * 8)));
dword = Get_NB32_DCT(dev, dct, 0x27c); dword = Get_NB32_DCT(dev, dct, 0x27c);
dword |= 0xff; /* EccMask = 0xff */ dword |= 0xff; /* EccMask = 0xff */
Set_NB32_DCT(dev, dct, 0x27c, dword); Set_NB32_DCT(dev, dct, 0x27c, dword);