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mb/intel/jasperlake_rvp: Skip CPU Replacement Check for jasperlake rvp 

This patch enables the SkipCpuReplacementCheck config for jasperlake rvp
to avoid the forced MRC training with the soldered down SOC.

BUG=b:160201335
BRANCH=None
TEST=Build and verify on jasperlake rvp with CSE Lite SKU.
Cq-Depend: chrome-internal:3142530

Change-Id: I40fb9a25170e8db3c63a71428ba459160a918961
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43146
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Krishna Prasad Bhat 2020-07-06 21:44:54 +05:30 committed by Karthik Ramasubramanian
parent c529e6ca7c
commit 21b303dc54
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
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@ -55,6 +55,9 @@ chip soc/intel/jasperlake
# EC memory map range is 0x900-0x9ff # EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901" register "gen3_dec" = "0x00fc0901"
# Skip the CPU repalcement check
register "SkipCpuReplacementCheck" = "1"
register "PchHdaDspEnable" = "1" register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHdaEnable" = "0" register "PchHdaAudioLinkHdaEnable" = "0"
register "PchHdaAudioLinkSspEnable[0]" = "1" register "PchHdaAudioLinkSspEnable[0]" = "1"