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src/southbridge/amd/sr5650: Always configure lane director on startup 

On the ASUS KGPE-D16 it was noted that the pin straps did not properly
configure the lane director hardware, causing link training failure
on NIC B.  Forcing coreboot to always reconfigure the lane director
on startup resolves this problem.

Change-Id: I5b78cef84960e0f42cc3e0406a7031d12d21f3ad
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12014
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Timothy Pearson 2015-07-03 17:16:22 -05:00 committed by Stefan Reinauer
parent a44daac7e6
commit 21be0d2bd0
1 changed files with 3 additions and 10 deletions
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7
src/southbridge/amd/sr5650/pcie.c
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@ -858,8 +858,6 @@ void sr56x0_lock_hwinitreg(void)
void config_gpp_core(device_t nb_dev, device_t sb_dev)
{
u32 reg;
struct southbridge_amd_sr5650_config *cfg =
(struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
reg = nbmisc_read_index(nb_dev, 0x20);
if (AtiPcieCfg.Config & PCIE_ENABLE_STATIC_DEV_REMAP)
@ -875,13 +873,8 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev)
reg &= ~((1 << 31) | (1 << 15) | (1 << 13)); //De-asserts
nbmisc_write_index(nb_dev, 0x8, reg);
reg = nbmisc_read_index(nb_dev, 0x67); /* get STRAP_BIF_LINK_CONFIG at bit 0-4 */
if (cfg->gpp3a_configuration != (reg & 0x1F))
switching_gpp3a_configurations(nb_dev, sb_dev);
reg = nbmisc_read_index(nb_dev, 0x8); /* get MULTIPORT_CONFIG_GPP1 MULTIPORT_CONFIG_CONFIG_GPP2 at bit 8,9 */
if ((cfg->gpp1_configuration << 8) != (reg & (1 << 8)))
switching_gpp1_configurations(nb_dev, sb_dev);
if ((cfg->gpp2_configuration << 9) != (reg & (1 << 9)))
switching_gpp2_configurations(nb_dev, sb_dev);
ValidatePortEn(nb_dev);
}