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soc/intel/alderlake: add power limits for Alder Lake-M 282 SKU 

There are two different types of 282 SKU available with TDP
of 15W and 12W for Alder Lake-M SoC. This patch adds support
for these TDP values for 282 SKU as per document 643782.

BUG=None
BRANCH=None
TEST=Build FW and test on adlrvp board

Change-Id: I553b2362b7bf811e6bf02fd9d68f78c2caeb7398
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
This commit is contained in:
Sumeet Pawnikar 2021-09-30 10:04:41 +05:30 committed by Felix Held
parent e415df9b7f
commit 21c431b81d
2 changed files with 11 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/soc/intel/alderlake/chip.h
View File

@ -25,7 +25,8 @@ enum soc_intel_alderlake_power_limits {
ADL_P_482_CORE, ADL_P_482_CORE,
ADL_P_682_28W_CORE, ADL_P_682_28W_CORE,
ADL_P_682_45W_CORE, ADL_P_682_45W_CORE,
ADL_M_282_CORE, ADL_M_282_12W_CORE,
ADL_M_282_15W_CORE,
ADL_M_242_CORE, ADL_M_242_CORE,
ADL_P_242_CORE, ADL_P_242_CORE,
ADL_POWER_LIMITS_COUNT ADL_POWER_LIMITS_COUNT
@ -34,6 +35,7 @@ enum soc_intel_alderlake_power_limits {
/* TDP values for different SKUs */ /* TDP values for different SKUs */
enum soc_intel_alderlake_cpu_tdps { enum soc_intel_alderlake_cpu_tdps {
TDP_9W = 9, TDP_9W = 9,
TDP_12W = 12,
TDP_15W = 15, TDP_15W = 15,
TDP_28W = 28, TDP_28W = 28,
TDP_45W = 45 TDP_45W = 45
@ -50,7 +52,8 @@ static const struct {
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_482_CORE, TDP_28W }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_482_CORE, TDP_28W },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_45W_CORE, TDP_45W }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_45W_CORE, TDP_45W },
{ PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_CORE, TDP_15W }, { PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W },
{ PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W },
{ PCI_DEVICE_ID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W }, { PCI_DEVICE_ID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W },
}; };

7
src/soc/intel/alderlake/chipset.cb
View File

@ -26,7 +26,12 @@ chip soc/intel/alderlake
.tdp_pl4 = 215, .tdp_pl4 = 215,
}" }"
register "power_limits_config[ADL_M_282_CORE]" = "{ register "power_limits_config[ADL_M_282_12W_CORE]" = "{
.tdp_pl1_override = 12,
.tdp_pl2_override = 35,
}"
register "power_limits_config[ADL_M_282_15W_CORE]" = "{
.tdp_pl1_override = 15, .tdp_pl1_override = 15,
.tdp_pl2_override = 45, .tdp_pl2_override = 45,
}" }"