soc/intel/tigerlake: Add PCH-H GPIO definitions
Add TGL-H GPIO definitions, based on existing TGL definitions and how CNP/CNP-H handles the split. Reference: - Intel doc 619207 - TigerLake FSP - linux/drivers/pinctrl/intel/pinctrl-tigerlake.c Change-Id: If9a0fd1691fc1143b5c214a2613d270199367659 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Jeremy Soller
Felix Held
parent
657f7db769
commit
21d7c477a4
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@ -18,12 +18,10 @@ bootblock-y += bootblock/bootblock.c
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bootblock-y += bootblock/pch.c
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bootblock-y += bootblock/report_platform.c
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bootblock-y += espi.c
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bootblock-y += gpio.c
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bootblock-y += p2sb.c
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romstage-y += espi.c
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romstage-y += meminit.c
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romstage-y += gpio.c
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romstage-y += reset.c
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ramstage-y += acpi.c
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@ -34,7 +32,6 @@ ramstage-y += elog.c
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ramstage-y += espi.c
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ramstage-y += finalize.c
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ramstage-y += fsp_params.c
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ramstage-y += gpio.c
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ramstage-y += lockdown.c
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ramstage-y += me.c
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ramstage-y += p2sb.c
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@ -45,7 +42,6 @@ ramstage-y += systemagent.c
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ramstage-y += xhci.c
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ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog_lib.c
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smm-y += gpio.c
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smm-y += p2sb.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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@ -53,7 +49,19 @@ smm-y += uart.c
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smm-y += elog.c
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smm-y += xhci.c
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ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_PCH_H),y)
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bootblock-y += gpio_pch_h.c
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romstage-y += gpio_pch_h.c
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ramstage-y += gpio_pch_h.c
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smm-y += gpio_pch_h.c
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verstage-y += gpio_pch_h.c
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else
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bootblock-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += gpio.c
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smm-y += gpio.c
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verstage-y += gpio.c
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endif
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CPPFLAGS_common += -I$(src)/soc/intel/tigerlake
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CPPFLAGS_common += -I$(src)/soc/intel/tigerlake/include
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@ -0,0 +1,147 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <intelblocks/gpio.h>
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#include <soc/gpio_defs_pch_h.h>
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#include <soc/intel/common/acpi/gpio.asl>
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#include <soc/intel/common/block/acpi/acpi/gpio_op.asl>
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#include <soc/irq.h>
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#include <soc/pcr_ids.h>
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Device (GPIO)
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{
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Name (_HID, "INT34C6")
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Name (_UID, 0)
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Name (_DDN, "GPIO Controller")
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Name (RBUF, ResourceTemplate()
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{
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Memory32Fixed (ReadWrite, 0, 0, COM0)
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Memory32Fixed (ReadWrite, 0, 0, COM1)
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Memory32Fixed (ReadWrite, 0, 0, COM3)
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Memory32Fixed (ReadWrite, 0, 0, COM4)
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Memory32Fixed (ReadWrite, 0, 0, COM5)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
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{ GPIO_IRQ14 }
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})
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Method (_CRS, 0, NotSerialized)
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{
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/* GPIO Community 0 */
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CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
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CreateDWordField (^RBUF, ^COM0._LEN, LEN0)
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BAS0 = ^^PCRB (PID_GPIOCOM0)
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LEN0 = GPIO_BASE_SIZE
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/* GPIO Community 1 */
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CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
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CreateDWordField (^RBUF, ^COM1._LEN, LEN1)
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BAS1 = ^^PCRB (PID_GPIOCOM1)
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LEN1 = GPIO_BASE_SIZE
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/* GPIO Community 3 */
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CreateDWordField (^RBUF, ^COM3._BAS, BAS3)
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CreateDWordField (^RBUF, ^COM3._LEN, LEN3)
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BAS3 = ^^PCRB (PID_GPIOCOM3)
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LEN3 = GPIO_BASE_SIZE
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/* GPIO Community 4 */
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CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
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CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
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BAS4 = ^^PCRB (PID_GPIOCOM4)
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LEN4 = GPIO_BASE_SIZE
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/* GPIO Community 5 */
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CreateDWordField (^RBUF, ^COM5._BAS, BAS5)
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CreateDWordField (^RBUF, ^COM5._LEN, LEN5)
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BAS5 = ^^PCRB (PID_GPIOCOM5)
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LEN5 = GPIO_BASE_SIZE
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Return (RBUF)
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}
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Method (_STA, 0, NotSerialized)
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{
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Return (0xF)
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}
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}
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/*
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* Get GPIO DW0 Address
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* Arg0 - GPIO Number
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*/
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Method (GADD, 1, NotSerialized)
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{
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/* GPIO Community 0 */
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If (Arg0 >= GPIO_COM0_START && Arg0 <= GPIO_COM0_END)
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{
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Local0 = PID_GPIOCOM0
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Local1 = Arg0 - GPIO_COM0_START
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}
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/* GPIO Community 1 */
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If (Arg0 >= GPIO_COM1_START && Arg0 <= GPIO_COM1_END)
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{
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Local0 = PID_GPIOCOM1
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Local1 = Arg0 - GPIO_COM1_START
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}
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/* GPIO Community 2 */
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If (Arg0 >= GPIO_COM2_START && Arg0 <= GPIO_COM2_END)
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{
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Local0 = PID_GPIOCOM2
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Local1 = Arg0 - GPIO_COM2_START
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}
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/* GPIO Community 3 */
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If (Arg0 >= GPIO_COM3_START && Arg0 <= GPIO_COM3_END)
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{
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Local0 = PID_GPIOCOM3
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Local1 = Arg0 - GPIO_COM3_START
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}
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/* GPIO Community 4 */
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If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END)
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{
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Local0 = PID_GPIOCOM4
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Local1 = Arg0 - GPIO_COM4_START
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}
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/* GPIO Community 05*/
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If (Arg0 >= GPIO_COM5_START && Arg0 <= GPIO_COM5_END)
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{
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Local0 = PID_GPIOCOM5
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Local1 = Arg0 - GPIO_COM5_START
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}
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Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16)
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Return (Local2)
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}
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/*
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* Return PCR Port ID of GPIO Communities
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*
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* Arg0: GPIO Community (0-5)
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*/
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Method (GPID, 1, Serialized)
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{
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Switch (ToInteger (Arg0))
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{
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Case (COMM_0) {
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Local0 = PID_GPIOCOM0
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}
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Case (COMM_1) {
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Local0 = PID_GPIOCOM1
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}
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Case (COMM_2) {
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Local0 = PID_GPIOCOM2
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}
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Case (COMM_3) {
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Local0 = PID_GPIOCOM3
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}
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Case (COMM_4) {
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Local0 = PID_GPIOCOM4
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}
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Case (COMM_5) {
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Local0 = PID_GPIOCOM5
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}
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Default {
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Return (0)
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}
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}
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Return (Local0)
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}
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@ -12,7 +12,11 @@
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#include "camera_clock_ctl.asl"
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/* GPIO controller */
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#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
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#include "gpio_pch_h.asl"
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#else
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#include "gpio.asl"
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#endif
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/* ESPI 0:1f.0 */
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#include <soc/intel/common/block/acpi/acpi/lpc.asl>
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@ -20,7 +20,7 @@
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#include <intelblocks/xdci.h>
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#include <intelpch/lockdown.h>
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#include <security/vboot/vboot_common.h>
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#include <soc/gpio_soc_defs.h>
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#include <soc/gpio.h>
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#include <soc/intel/common/vbt.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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@ -0,0 +1,218 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <intelblocks/gpio.h>
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#include <intelblocks/pcr.h>
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#include <soc/pcr_ids.h>
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#include <soc/pmc.h>
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/*
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* This file is created based on Intel Tiger Lake Processor PCH Datasheet
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* Document number: 619207
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* Chapter number: 27
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*/
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static const struct reset_mapping rst_map[] = {
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{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
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};
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static const struct reset_mapping rst_map_com2[] = {
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{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
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};
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/*
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* The GPIO pinctrl driver for Tiger Lake on Linux expects 32 GPIOs per pad
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* group, regardless of whether or not there is a physical pad for each
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* exposed GPIO number.
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*
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* This results in the OS having a sparse GPIO map, and devices that need
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* to export an ACPI GPIO must use the OS expected number.
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*
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* Not all pins are usable as GPIO and those groups do not have a pad base.
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*
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* This layout matches the Linux kernel pinctrl map for TGL-H at:
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* linux/drivers/pinctrl/intel/pinctrl-tigerlake.c
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*/
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static const struct pad_group tgl_community0_groups[] = {
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INTEL_GPP_BASE(GPIO_COM0_START, GPP_SPI0_IO_2, GPP_ESPI_CLK_LOOPBK, 0), /* GPP_A */
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INTEL_GPP_BASE(GPIO_COM0_START, GPP_R0, GPP_R19, 32), /* GPP_R */
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INTEL_GPP_BASE(GPIO_COM0_START, GPP_B0, GPP_GSPI1_CLK_LOOPBK, 64), /* GPP_B */
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INTEL_GPP_BASE(GPIO_COM0_START, ESPI_USB_OCB_0, USB_CPU_OCB_3, 96), /* vGPIO_0 */
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};
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static const struct pad_group tgl_community1_groups[] = {
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INTEL_GPP_BASE(GPIO_COM1_START, GPP_D0, GPP_GSPI3_CLK_LOOPBK, 128), /* GPP_D */
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INTEL_GPP_BASE(GPIO_COM1_START, GPP_C0, GPP_C23, 160), /* GPP_C */
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INTEL_GPP_BASE(GPIO_COM1_START, GPP_S0, GPP_S7, 192), /* GPP_S */
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INTEL_GPP_BASE(GPIO_COM1_START, GPP_G0, GPP_GSPI2_CLK_LOOPBK, 224), /* GPP_G */
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INTEL_GPP_BASE(GPIO_COM1_START, CNV_BTEN, vI2S2_RXD, 256), /* vGPIO */
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};
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/* This community is not visible to the OS */
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static const struct pad_group tgl_community2_groups[] = {
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INTEL_GPP(GPIO_COM2_START, GPD0, GPD12), /* GPD */
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};
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static const struct pad_group tgl_community3_groups[] = {
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INTEL_GPP_BASE(GPIO_COM3_START, GPP_E0, GPP_E12, 288), /* GPP_E */
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INTEL_GPP_BASE(GPIO_COM3_START, GPP_F0, GPP_F23, 320), /* GPP_F */
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};
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static const struct pad_group tgl_community4_groups[] = {
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INTEL_GPP_BASE(GPIO_COM4_START, GPP_H0, GPP_H23, 352), /* GPP_H */
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INTEL_GPP_BASE(GPIO_COM4_START, GPP_J0, GPP_J9, 384), /* GPP_J */
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INTEL_GPP_BASE(GPIO_COM4_START, GPP_K0, GPP_MLK_RSTB, 416), /* GPP_K */
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};
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static const struct pad_group tgl_community5_groups[] = {
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INTEL_GPP_BASE(GPIO_COM5_START, GPP_I0, GPP_I14, 448), /* GPP_I */
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INTEL_GPP(GPIO_COM5_START, GPP_JTAG_TDO, GPP_JTAG_CPU_TRSTB), /* JTAG */
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};
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static const struct pad_community tgl_communities[] = {
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[COMM_0] = { /* GPP A, R, B, vGPIO_0 */
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.port = PID_GPIOCOM0,
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.first_pad = GPIO_COM0_START,
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.last_pad = GPIO_COM0_END,
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.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_int_sts_reg_0 = GPI_INT_STS_0,
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.gpi_int_en_reg_0 = GPI_INT_EN_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPP_ARB",
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.acpi_path = "\\_SB.PCI0.GPIO",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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.groups = tgl_community0_groups,
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.num_groups = ARRAY_SIZE(tgl_community0_groups),
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},
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[COMM_1] = { /* GPP D, C, S, G, vGPIO */
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.port = PID_GPIOCOM1,
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.first_pad = GPIO_COM1_START,
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.last_pad = GPIO_COM1_END,
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.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_int_sts_reg_0 = GPI_INT_STS_0,
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.gpi_int_en_reg_0 = GPI_INT_EN_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPP_DCSG",
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.acpi_path = "\\_SB.PCI0.GPIO",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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.groups = tgl_community1_groups,
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.num_groups = ARRAY_SIZE(tgl_community1_groups),
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},
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[COMM_2] = { /* GPD */
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.port = PID_GPIOCOM2,
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.first_pad = GPIO_COM2_START,
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.last_pad = GPIO_COM2_END,
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.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_int_sts_reg_0 = GPI_INT_STS_0,
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.gpi_int_en_reg_0 = GPI_INT_EN_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPD",
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.acpi_path = "\\_SB.PCI0.GPIO",
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.reset_map = rst_map_com2,
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.num_reset_vals = ARRAY_SIZE(rst_map_com2),
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.groups = tgl_community2_groups,
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.num_groups = ARRAY_SIZE(tgl_community2_groups),
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},
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[COMM_3] = { /* GPP E, F */
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.port = PID_GPIOCOM3,
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.first_pad = GPIO_COM3_START,
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.last_pad = GPIO_COM3_END,
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.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_int_sts_reg_0 = GPI_INT_STS_0,
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.gpi_int_en_reg_0 = GPI_INT_EN_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPP_EF",
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.acpi_path = "\\_SB.PCI0.GPIO",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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.groups = tgl_community3_groups,
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.num_groups = ARRAY_SIZE(tgl_community3_groups),
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},
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[COMM_4] = { /* GPP H, J, K */
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.port = PID_GPIOCOM4,
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.first_pad = GPIO_COM4_START,
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.last_pad = GPIO_COM4_END,
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.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_int_sts_reg_0 = GPI_INT_STS_0,
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.gpi_int_en_reg_0 = GPI_INT_EN_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
|
||||
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
|
||||
.name = "GPP_HJK",
|
||||
.acpi_path = "\\_SB.PCI0.GPIO",
|
||||
.reset_map = rst_map,
|
||||
.num_reset_vals = ARRAY_SIZE(rst_map),
|
||||
.groups = tgl_community4_groups,
|
||||
.num_groups = ARRAY_SIZE(tgl_community4_groups),
|
||||
},
|
||||
[COMM_5] = { /* GPP I, JTAG */
|
||||
.port = PID_GPIOCOM5,
|
||||
.first_pad = GPIO_COM5_START,
|
||||
.last_pad = GPIO_COM5_END,
|
||||
.num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
|
||||
.pad_cfg_base = PAD_CFG_BASE,
|
||||
.host_own_reg_0 = HOSTSW_OWN_REG_0,
|
||||
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
|
||||
.gpi_int_en_reg_0 = GPI_INT_EN_0,
|
||||
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
|
||||
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
|
||||
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
|
||||
.name = "GPP_I",
|
||||
.acpi_path = "\\_SB.PCI0.GPIO",
|
||||
.reset_map = rst_map,
|
||||
.num_reset_vals = ARRAY_SIZE(rst_map),
|
||||
.groups = tgl_community5_groups,
|
||||
.num_groups = ARRAY_SIZE(tgl_community5_groups),
|
||||
},
|
||||
};
|
||||
|
||||
const struct pad_community *soc_gpio_get_community(size_t *num_communities)
|
||||
{
|
||||
*num_communities = ARRAY_SIZE(tgl_communities);
|
||||
return tgl_communities;
|
||||
}
|
||||
|
||||
const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
|
||||
{
|
||||
static const struct pmc_to_gpio_route routes[] = {
|
||||
{ PMC_GPD, GPD },
|
||||
{ PMC_GPP_A, GPP_A },
|
||||
{ PMC_GPP_B, GPP_B },
|
||||
{ PMC_GPP_C, GPP_C },
|
||||
{ PMC_GPP_D, GPP_D },
|
||||
{ PMC_GPP_E, GPP_E },
|
||||
{ PMC_GPP_F, GPP_F },
|
||||
{ PMC_GPP_G, GPP_G },
|
||||
{ PMC_GPP_H, GPP_H },
|
||||
{ PMC_GPP_I, GPP_I },
|
||||
{ PMC_GPP_J, GPP_J },
|
||||
{ PMC_GPP_K, GPP_K },
|
||||
{ PMC_GPP_R, GPP_R },
|
||||
{ PMC_GPP_S, GPP_S },
|
||||
};
|
||||
*num = ARRAY_SIZE(routes);
|
||||
return routes;
|
||||
}
|
||||
|
|
@ -3,10 +3,13 @@
|
|||
#ifndef _SOC_TIGERLAKE_GPIO_H_
|
||||
#define _SOC_TIGERLAKE_GPIO_H_
|
||||
|
||||
#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
|
||||
#include <soc/gpio_defs_pch_h.h>
|
||||
#else
|
||||
#include <soc/gpio_defs.h>
|
||||
#include <intelblocks/gpio.h>
|
||||
|
||||
#define CROS_GPIO_DEVICE_NAME "INT34C5:00"
|
||||
#endif
|
||||
#include <intelblocks/gpio.h>
|
||||
|
||||
/* Enable GPIO community power management configuration */
|
||||
#define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPVNNREQEN | \
|
||||
|
|
|
|||
|
|
@ -0,0 +1,315 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _SOC_TIGERLAKE_GPIO_DEFS_PCH_H_H_
|
||||
#define _SOC_TIGERLAKE_GPIO_DEFS_PCH_H_H_
|
||||
|
||||
#ifndef __ACPI__
|
||||
#include <stddef.h>
|
||||
#endif
|
||||
#include <soc/gpio_soc_defs_pch_h.h>
|
||||
|
||||
#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */
|
||||
|
||||
#define NUM_GPIO_COMx_GPI_REGS(n) \
|
||||
(ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
|
||||
|
||||
#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
|
||||
#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
|
||||
#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)
|
||||
#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS)
|
||||
#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)
|
||||
#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS)
|
||||
|
||||
#define NUM_GPI_STATUS_REGS \
|
||||
((NUM_GPIO_COM0_GPI_REGS) +\
|
||||
(NUM_GPIO_COM1_GPI_REGS) +\
|
||||
(NUM_GPIO_COM2_GPI_REGS) +\
|
||||
(NUM_GPIO_COM3_GPI_REGS) +\
|
||||
(NUM_GPIO_COM4_GPI_REGS) +\
|
||||
(NUM_GPIO_COM5_GPI_REGS))
|
||||
/*
|
||||
* IOxAPIC IRQs for the GPIOs
|
||||
*/
|
||||
|
||||
/* Group A */
|
||||
#define GPP_A0_IRQ 0x18
|
||||
#define GPP_A1_IRQ 0x19
|
||||
#define GPP_A2_IRQ 0x1A
|
||||
#define GPP_A3_IRQ 0x1B
|
||||
#define GPP_A4_IRQ 0x1C
|
||||
#define GPP_A5_IRQ 0x1D
|
||||
#define GPP_A6_IRQ 0x1E
|
||||
#define GPP_A7_IRQ 0x1F
|
||||
#define GPP_A8_IRQ 0x20
|
||||
#define GPP_A9_IRQ 0x21
|
||||
#define GPP_A10_IRQ 0x22
|
||||
#define GPP_A11_IRQ 0x23
|
||||
#define GPP_A12_IRQ 0x24
|
||||
#define GPP_A13_IRQ 0x25
|
||||
#define GPP_A14_IRQ 0x26
|
||||
#define GPP_A15_IRQ 0x27
|
||||
#define GPP_A16_IRQ 0x28
|
||||
#define GPP_A17_IRQ 0x29
|
||||
#define GPP_A18_IRQ 0x2A
|
||||
#define GPP_A19_IRQ 0x2B
|
||||
#define GPP_A20_IRQ 0x2C
|
||||
#define GPP_A21_IRQ 0x2D
|
||||
#define GPP_A22_IRQ 0x2E
|
||||
#define GPP_A23_IRQ 0x2F
|
||||
|
||||
/* Group R */
|
||||
#define GPP_R0_IRQ 0x37
|
||||
#define GPP_R1_IRQ 0x38
|
||||
#define GPP_R2_IRQ 0x39
|
||||
#define GPP_R3_IRQ 0x3A
|
||||
#define GPP_R4_IRQ 0x3B
|
||||
#define GPP_R5_IRQ 0x3C
|
||||
#define GPP_R6_IRQ 0x3D
|
||||
#define GPP_R7_IRQ 0x3E
|
||||
|
||||
/* Group B */
|
||||
#define GPP_B0_IRQ 0x30
|
||||
#define GPP_B1_IRQ 0x31
|
||||
#define GPP_B2_IRQ 0x32
|
||||
#define GPP_B3_IRQ 0x33
|
||||
#define GPP_B4_IRQ 0x34
|
||||
#define GPP_B5_IRQ 0x35
|
||||
#define GPP_B6_IRQ 0x36
|
||||
#define GPP_B7_IRQ 0x37
|
||||
#define GPP_B8_IRQ 0x38
|
||||
#define GPP_B9_IRQ 0x39
|
||||
#define GPP_B10_IRQ 0x3A
|
||||
#define GPP_B11_IRQ 0x3B
|
||||
#define GPP_B12_IRQ 0x3C
|
||||
#define GPP_B13_IRQ 0x3D
|
||||
#define GPP_B14_IRQ 0x3E
|
||||
#define GPP_B15_IRQ 0x3F
|
||||
#define GPP_B16_IRQ 0x40
|
||||
#define GPP_B17_IRQ 0x41
|
||||
#define GPP_B18_IRQ 0x42
|
||||
#define GPP_B19_IRQ 0x43
|
||||
#define GPP_B20_IRQ 0x44
|
||||
#define GPP_B21_IRQ 0x45
|
||||
#define GPP_B22_IRQ 0x46
|
||||
#define GPP_B23_IRQ 0x47
|
||||
|
||||
/* Group C */
|
||||
#define GPP_C0_IRQ 0x48
|
||||
#define GPP_C1_IRQ 0x49
|
||||
#define GPP_C2_IRQ 0x4A
|
||||
#define GPP_C3_IRQ 0x4B
|
||||
#define GPP_C4_IRQ 0x4C
|
||||
#define GPP_C5_IRQ 0x4D
|
||||
#define GPP_C6_IRQ 0x4E
|
||||
#define GPP_C7_IRQ 0x4F
|
||||
#define GPP_C8_IRQ 0x50
|
||||
#define GPP_C9_IRQ 0x51
|
||||
#define GPP_C10_IRQ 0x52
|
||||
#define GPP_C11_IRQ 0x53
|
||||
#define GPP_C12_IRQ 0x54
|
||||
#define GPP_C13_IRQ 0x55
|
||||
#define GPP_C14_IRQ 0x56
|
||||
#define GPP_C15_IRQ 0x57
|
||||
#define GPP_C16_IRQ 0x58
|
||||
#define GPP_C17_IRQ 0x59
|
||||
#define GPP_C18_IRQ 0x5A
|
||||
#define GPP_C19_IRQ 0x5B
|
||||
#define GPP_C20_IRQ 0x5C
|
||||
#define GPP_C21_IRQ 0x5D
|
||||
#define GPP_C22_IRQ 0x5E
|
||||
#define GPP_C23_IRQ 0x5F
|
||||
|
||||
/* Group D */
|
||||
#define GPP_D0_IRQ 0x60
|
||||
#define GPP_D1_IRQ 0x61
|
||||
#define GPP_D2_IRQ 0x62
|
||||
#define GPP_D3_IRQ 0x63
|
||||
#define GPP_D4_IRQ 0x64
|
||||
#define GPP_D5_IRQ 0x65
|
||||
#define GPP_D6_IRQ 0x66
|
||||
#define GPP_D7_IRQ 0x67
|
||||
#define GPP_D8_IRQ 0x68
|
||||
#define GPP_D9_IRQ 0x69
|
||||
#define GPP_D10_IRQ 0x6A
|
||||
#define GPP_D11_IRQ 0x6B
|
||||
#define GPP_D12_IRQ 0x6C
|
||||
#define GPP_D13_IRQ 0x6D
|
||||
#define GPP_D14_IRQ 0x6E
|
||||
#define GPP_D15_IRQ 0x6F
|
||||
#define GPP_D16_IRQ 0x70
|
||||
#define GPP_D17_IRQ 0x71
|
||||
#define GPP_D18_IRQ 0x72
|
||||
#define GPP_D19_IRQ 0x73
|
||||
#define GPP_D20_IRQ 0x74
|
||||
#define GPP_D21_IRQ 0x75
|
||||
#define GPP_D22_IRQ 0x76
|
||||
#define GPP_D23_IRQ 0x77
|
||||
|
||||
/* Group S */
|
||||
#define GPP_S0_IRQ 0x3F
|
||||
#define GPP_S1_IRQ 0x40
|
||||
#define GPP_S2_IRQ 0x41
|
||||
#define GPP_S3_IRQ 0x42
|
||||
#define GPP_S4_IRQ 0x43
|
||||
#define GPP_S5_IRQ 0x44
|
||||
#define GPP_S6_IRQ 0x45
|
||||
#define GPP_S7_IRQ 0x46
|
||||
|
||||
/* Group G */
|
||||
#define GPP_G0_IRQ 0x18
|
||||
#define GPP_G1_IRQ 0x19
|
||||
#define GPP_G2_IRQ 0x1A
|
||||
#define GPP_G3_IRQ 0x1B
|
||||
#define GPP_G4_IRQ 0x1C
|
||||
#define GPP_G5_IRQ 0x1D
|
||||
#define GPP_G6_IRQ 0x1E
|
||||
#define GPP_G7_IRQ 0x1F
|
||||
#define GPP_G8_IRQ 0x20
|
||||
#define GPP_G9_IRQ 0x21
|
||||
#define GPP_G10_IRQ 0x22
|
||||
#define GPP_G11_IRQ 0x23
|
||||
#define GPP_G12_IRQ 0x24
|
||||
#define GPP_G13_IRQ 0x25
|
||||
#define GPP_G14_IRQ 0x26
|
||||
#define GPP_G15_IRQ 0x27
|
||||
|
||||
/* Group VGPIO */
|
||||
#define VGPIO4_IRQ 0x28
|
||||
|
||||
/* Group GPD */
|
||||
#define GPD0_IRQ 0x29
|
||||
#define GPD1_IRQ 0x2A
|
||||
#define GPD2_IRQ 0x2B
|
||||
#define GPD3_IRQ 0x2C
|
||||
#define GPD4_IRQ 0x2D
|
||||
#define GPD5_IRQ 0x2E
|
||||
#define GPD6_IRQ 0x2F
|
||||
#define GPD7_IRQ 0x30
|
||||
#define GPD8_IRQ 0x31
|
||||
#define GPD9_IRQ 0x32
|
||||
#define GPD10_IRQ 0x33
|
||||
#define GPD11_IRQ 0x34
|
||||
#define GPD12_IRQ 0x35
|
||||
|
||||
/* Group E */
|
||||
#define GPP_E0_IRQ 0x35
|
||||
#define GPP_E1_IRQ 0x36
|
||||
#define GPP_E2_IRQ 0x37
|
||||
#define GPP_E3_IRQ 0x38
|
||||
#define GPP_E4_IRQ 0x39
|
||||
#define GPP_E5_IRQ 0x3A
|
||||
#define GPP_E6_IRQ 0x3B
|
||||
#define GPP_E7_IRQ 0x3C
|
||||
#define GPP_E8_IRQ 0x3D
|
||||
#define GPP_E9_IRQ 0x3E
|
||||
#define GPP_E10_IRQ 0x3F
|
||||
#define GPP_E11_IRQ 0x40
|
||||
#define GPP_E12_IRQ 0x41
|
||||
|
||||
/* Group F */
|
||||
#define GPP_F0_IRQ 0x42
|
||||
#define GPP_F1_IRQ 0x43
|
||||
#define GPP_F2_IRQ 0x44
|
||||
#define GPP_F3_IRQ 0x45
|
||||
#define GPP_F4_IRQ 0x46
|
||||
#define GPP_F5_IRQ 0x47
|
||||
#define GPP_F6_IRQ 0x48
|
||||
#define GPP_F7_IRQ 0x49
|
||||
#define GPP_F8_IRQ 0x4A
|
||||
#define GPP_F9_IRQ 0x4B
|
||||
#define GPP_F10_IRQ 0x4C
|
||||
#define GPP_F11_IRQ 0x4D
|
||||
#define GPP_F12_IRQ 0x4E
|
||||
#define GPP_F13_IRQ 0x4F
|
||||
#define GPP_F14_IRQ 0x50
|
||||
#define GPP_F15_IRQ 0x51
|
||||
#define GPP_F16_IRQ 0x52
|
||||
#define GPP_F17_IRQ 0x53
|
||||
#define GPP_F18_IRQ 0x54
|
||||
#define GPP_F19_IRQ 0x55
|
||||
#define GPP_F20_IRQ 0x56
|
||||
#define GPP_F21_IRQ 0x57
|
||||
#define GPP_F22_IRQ 0x58
|
||||
#define GPP_F23_IRQ 0x59
|
||||
|
||||
/* Group H */
|
||||
#define GPP_H0_IRQ 0x5A
|
||||
#define GPP_H1_IRQ 0x5B
|
||||
#define GPP_H2_IRQ 0x5C
|
||||
#define GPP_H3_IRQ 0x5D
|
||||
#define GPP_H4_IRQ 0x5E
|
||||
#define GPP_H5_IRQ 0x5F
|
||||
#define GPP_H6_IRQ 0x60
|
||||
#define GPP_H7_IRQ 0x61
|
||||
#define GPP_H8_IRQ 0x62
|
||||
#define GPP_H9_IRQ 0x63
|
||||
#define GPP_H10_IRQ 0x64
|
||||
#define GPP_H11_IRQ 0x65
|
||||
#define GPP_H12_IRQ 0x66
|
||||
#define GPP_H13_IRQ 0x67
|
||||
#define GPP_H14_IRQ 0x68
|
||||
#define GPP_H15_IRQ 0x69
|
||||
#define GPP_H16_IRQ 0x6A
|
||||
#define GPP_H17_IRQ 0x6B
|
||||
#define GPP_H18_IRQ 0x6C
|
||||
#define GPP_H19_IRQ 0x6D
|
||||
#define GPP_H20_IRQ 0x6E
|
||||
#define GPP_H21_IRQ 0x6F
|
||||
#define GPP_H22_IRQ 0x70
|
||||
#define GPP_H23_IRQ 0x71
|
||||
|
||||
/* Group K */
|
||||
#define GPP_K0_IRQ 0x72
|
||||
#define GPP_K1_IRQ 0x73
|
||||
#define GPP_K2_IRQ 0x74
|
||||
#define GPP_K3_IRQ 0x75
|
||||
#define GPP_K4_IRQ 0x76
|
||||
#define GPP_K5_IRQ 0x77
|
||||
#define GPP_K6_IRQ 0x18
|
||||
#define GPP_K7_IRQ 0x19
|
||||
#define GPP_K8_IRQ 0x1A
|
||||
#define GPP_K9_IRQ 0x1B
|
||||
#define GPP_K10_IRQ 0x1C
|
||||
#define GPP_K11_IRQ 0x1D
|
||||
|
||||
/* Group J */
|
||||
#define GPP_J0_IRQ 0x1E
|
||||
#define GPP_J1_IRQ 0x1F
|
||||
#define GPP_J2_IRQ 0x20
|
||||
#define GPP_J3_IRQ 0x21
|
||||
#define GPP_J4_IRQ 0x22
|
||||
#define GPP_J5_IRQ 0x23
|
||||
#define GPP_J6_IRQ 0x24
|
||||
#define GPP_J7_IRQ 0x25
|
||||
#define GPP_J8_IRQ 0x26
|
||||
#define GPP_J9_IRQ 0x27
|
||||
|
||||
/* Group I */
|
||||
#define GPP_I0_IRQ 0x28
|
||||
#define GPP_I1_IRQ 0x29
|
||||
#define GPP_I2_IRQ 0x2A
|
||||
#define GPP_I3_IRQ 0x2B
|
||||
#define GPP_I4_IRQ 0x2C
|
||||
#define GPP_I5_IRQ 0x2D
|
||||
#define GPP_I6_IRQ 0x2E
|
||||
#define GPP_I7_IRQ 0x2F
|
||||
#define GPP_I8_IRQ 0x30
|
||||
#define GPP_I9_IRQ 0x31
|
||||
#define GPP_I10_IRQ 0x32
|
||||
#define GPP_I11_IRQ 0x33
|
||||
#define GPP_I12_IRQ 0x34
|
||||
#define GPP_I13_IRQ 0x35
|
||||
#define GPP_I14_IRQ 0x36
|
||||
|
||||
/* Register defines. */
|
||||
#define GPIO_MISCCFG 0x10
|
||||
#define GPE_DW_SHIFT 8
|
||||
#define GPE_DW_MASK 0xfff00
|
||||
#define HOSTSW_OWN_REG_0 0xc0
|
||||
#define GPI_INT_STS_0 0x100
|
||||
#define GPI_INT_EN_0 0x120
|
||||
#define GPI_SMI_STS_0 0x180
|
||||
#define GPI_SMI_EN_0 0x1A0
|
||||
#define PAD_CFG_BASE 0x600
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,406 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_PCH_H_H_
|
||||
#define _SOC_TIGERLAKE_GPIO_SOC_DEFS_PCH_H_H_
|
||||
|
||||
/*
|
||||
* Most of the fixed numbers and macros are based on the GPP groups.
|
||||
* The GPIO groups are accessed through register blocks called
|
||||
* communities.
|
||||
* These values come from the FSP and match the PMC values for simplicity
|
||||
*/
|
||||
#define GPD 0x0
|
||||
#define GPP_A 0x1
|
||||
#define GPP_R 0x2
|
||||
#define GPP_B 0x3
|
||||
#define GPP_D 0x4
|
||||
#define GPP_C 0x5
|
||||
#define GPP_S 0x6
|
||||
#define GPP_G 0x7
|
||||
#define GPP_E 0x9
|
||||
#define GPP_F 0xA
|
||||
#define GPP_H 0xB
|
||||
#define GPP_J 0xC
|
||||
#define GPP_K 0xD
|
||||
#define GPP_I 0xE
|
||||
|
||||
#define GPIO_MAX_NUM_PER_GROUP 26
|
||||
|
||||
#define COMM_0 0
|
||||
#define COMM_1 1
|
||||
#define COMM_2 2
|
||||
#define COMM_3 3
|
||||
#define COMM_4 4
|
||||
#define COMM_5 5
|
||||
|
||||
/*
|
||||
* GPIOs are ordered monotonically increasing to match ACPI/OS driver.
|
||||
* See tglh_pins in linux/drivers/pinctrl/intel/pinctrl-tigerlake.c
|
||||
*/
|
||||
/* Group A */
|
||||
#define GPP_SPI0_IO_2 0
|
||||
#define GPP_SPI0_IO_3 1
|
||||
#define GPP_SPI0_MOSI_IO_0 2
|
||||
#define GPP_SPI0_MISO_IO_1 3
|
||||
#define GPP_SPI0_TPM_CSB 4
|
||||
#define GPP_SPI0_FLASH_0_CSB 5
|
||||
#define GPP_SPI0_FLASH_1_CSB 6
|
||||
#define GPP_SPI0_CLK 7
|
||||
#define GPP_A0 8
|
||||
#define GPP_A1 9
|
||||
#define GPP_A2 10
|
||||
#define GPP_A3 11
|
||||
#define GPP_A4 12
|
||||
#define GPP_A5 13
|
||||
#define GPP_A6 14
|
||||
#define GPP_A7 15
|
||||
#define GPP_A8 16
|
||||
#define GPP_A9 17
|
||||
#define GPP_A10 18
|
||||
#define GPP_A11 19
|
||||
#define GPP_A12 20
|
||||
#define GPP_A13 21
|
||||
#define GPP_A14 22
|
||||
#define GPP_SPI0_CLK_LOOPBK 23
|
||||
#define GPP_ESPI_CLK_LOOPBK 24
|
||||
|
||||
/* Group R */
|
||||
#define GPP_R0 25
|
||||
#define GPP_R1 26
|
||||
#define GPP_R2 27
|
||||
#define GPP_R3 28
|
||||
#define GPP_R4 29
|
||||
#define GPP_R5 30
|
||||
#define GPP_R6 31
|
||||
#define GPP_R7 32
|
||||
#define GPP_R8 33
|
||||
#define GPP_R9 34
|
||||
#define GPP_R10 35
|
||||
#define GPP_R11 36
|
||||
#define GPP_R12 37
|
||||
#define GPP_R13 38
|
||||
#define GPP_R14 39
|
||||
#define GPP_R15 40
|
||||
#define GPP_R16 41
|
||||
#define GPP_R17 42
|
||||
#define GPP_R18 43
|
||||
#define GPP_R19 44
|
||||
|
||||
/* Group B */
|
||||
#define GPP_B0 45
|
||||
#define GPP_B1 46
|
||||
#define GPP_B2 47
|
||||
#define GPP_B3 48
|
||||
#define GPP_B4 49
|
||||
#define GPP_B5 50
|
||||
#define GPP_B6 51
|
||||
#define GPP_B7 52
|
||||
#define GPP_B8 53
|
||||
#define GPP_B9 54
|
||||
#define GPP_B10 55
|
||||
#define GPP_B11 56
|
||||
#define GPP_B12 57
|
||||
#define GPP_B13 58
|
||||
#define GPP_B14 59
|
||||
#define GPP_B15 60
|
||||
#define GPP_B16 61
|
||||
#define GPP_B17 62
|
||||
#define GPP_B18 63
|
||||
#define GPP_B19 64
|
||||
#define GPP_B20 65
|
||||
#define GPP_B21 66
|
||||
#define GPP_B22 67
|
||||
#define GPP_B23 68
|
||||
#define GPP_GSPI0_CLK_LOOPBK 69
|
||||
#define GPP_GSPI1_CLK_LOOPBK 70
|
||||
|
||||
/* Group vGPIO_0 */
|
||||
#define ESPI_USB_OCB_0 71
|
||||
#define ESPI_USB_OCB_1 72
|
||||
#define ESPI_USB_OCB_2 73
|
||||
#define ESPI_USB_OCB_3 74
|
||||
#define USB_CPU_OCB_0 75
|
||||
#define USB_CPU_OCB_1 76
|
||||
#define USB_CPU_OCB_2 77
|
||||
#define USB_CPU_OCB_3 78
|
||||
|
||||
|
||||
#define GPIO_COM0_START GPP_SPI0_IO_2
|
||||
#define GPIO_COM0_END USB_CPU_OCB_3
|
||||
#define NUM_GPIO_COM0_PADS (GPIO_COM0_START - GPIO_COM0_END + 1)
|
||||
|
||||
/* Group D */
|
||||
#define GPP_D0 79
|
||||
#define GPP_D1 80
|
||||
#define GPP_D2 81
|
||||
#define GPP_D3 82
|
||||
#define GPP_D4 83
|
||||
#define GPP_D5 84
|
||||
#define GPP_D6 85
|
||||
#define GPP_D7 86
|
||||
#define GPP_D8 87
|
||||
#define GPP_D9 88
|
||||
#define GPP_D10 89
|
||||
#define GPP_D11 90
|
||||
#define GPP_D12 91
|
||||
#define GPP_D13 92
|
||||
#define GPP_D14 93
|
||||
#define GPP_D15 94
|
||||
#define GPP_D16 95
|
||||
#define GPP_D17 96
|
||||
#define GPP_D18 97
|
||||
#define GPP_D19 98
|
||||
#define GPP_D20 99
|
||||
#define GPP_D21 100
|
||||
#define GPP_D22 101
|
||||
#define GPP_D23 102
|
||||
#define GPP_SPI1_CLK_LOOPBK 103
|
||||
#define GPP_GSPI3_CLK_LOOPBK 104
|
||||
|
||||
/* Group C */
|
||||
#define GPP_C0 105
|
||||
#define GPP_C1 106
|
||||
#define GPP_C2 107
|
||||
#define GPP_C3 108
|
||||
#define GPP_C4 109
|
||||
#define GPP_C5 110
|
||||
#define GPP_C6 111
|
||||
#define GPP_C7 112
|
||||
#define GPP_C8 113
|
||||
#define GPP_C9 114
|
||||
#define GPP_C10 115
|
||||
#define GPP_C11 116
|
||||
#define GPP_C12 117
|
||||
#define GPP_C13 118
|
||||
#define GPP_C14 119
|
||||
#define GPP_C15 120
|
||||
#define GPP_C16 121
|
||||
#define GPP_C17 122
|
||||
#define GPP_C18 123
|
||||
#define GPP_C19 124
|
||||
#define GPP_C20 125
|
||||
#define GPP_C21 126
|
||||
#define GPP_C22 127
|
||||
#define GPP_C23 128
|
||||
|
||||
/* Group S */
|
||||
#define GPP_S0 129
|
||||
#define GPP_S1 130
|
||||
#define GPP_S2 131
|
||||
#define GPP_S3 132
|
||||
#define GPP_S4 133
|
||||
#define GPP_S5 134
|
||||
#define GPP_S6 135
|
||||
#define GPP_S7 136
|
||||
|
||||
/* Group G */
|
||||
#define GPP_G0 137
|
||||
#define GPP_G1 138
|
||||
#define GPP_G2 139
|
||||
#define GPP_G3 140
|
||||
#define GPP_G4 141
|
||||
#define GPP_G5 142
|
||||
#define GPP_G6 143
|
||||
#define GPP_G7 144
|
||||
#define GPP_G8 145
|
||||
#define GPP_G9 146
|
||||
#define GPP_G10 147
|
||||
#define GPP_G11 148
|
||||
#define GPP_G12 149
|
||||
#define GPP_G13 150
|
||||
#define GPP_G14 151
|
||||
#define GPP_G15 152
|
||||
#define GPP_GSPI2_CLK_LOOPBK 153
|
||||
|
||||
/* Group vGPIO */
|
||||
#define CNV_BTEN 154
|
||||
#define CNV_BT_HOST_WAKEB 155
|
||||
#define CNV_BT_IF_SELECT 156
|
||||
#define vCNV_BT_UART_TXD 157
|
||||
#define vCNV_BT_UART_RXD 158
|
||||
#define vCNV_BT_UART_CTS_B 159
|
||||
#define vCNV_BT_UART_RTS_B 160
|
||||
#define vCNV_MFUART1_TXD 161
|
||||
#define vCNV_MFUART1_RXD 162
|
||||
#define vCNV_MFUART1_CTS_B 163
|
||||
#define vCNV_MFUART1_RTS_B 164
|
||||
#define vUART0_TXD 165
|
||||
#define vUART0_RXD 166
|
||||
#define vUART0_CTS_B 167
|
||||
#define vUART0_RTS_B 168
|
||||
#define vISH_UART0_TXD 169
|
||||
#define vISH_UART0_RXD 170
|
||||
#define vISH_UART0_CTS_B 171
|
||||
#define vISH_UART0_RTS_B 172
|
||||
#define vCNV_BT_I2S_BCLK 173
|
||||
#define vCNV_BT_I2S_WS_SYNC 174
|
||||
#define vCNV_BT_I2S_SDO 175
|
||||
#define vCNV_BT_I2S_SDI 176
|
||||
#define vI2S2_SCLK 177
|
||||
#define vI2S2_SFRM 178
|
||||
#define vI2S2_TXD 179
|
||||
#define vI2S2_RXD 180
|
||||
|
||||
#define GPIO_COM1_START GPP_D0
|
||||
#define GPIO_COM1_END vI2S2_RXD
|
||||
#define NUM_GPIO_COM1_PADS (GPIO_COM1_END - GPIO_COM1_START + 1)
|
||||
|
||||
/* Group E */
|
||||
#define GPP_E0 181
|
||||
#define GPP_E1 182
|
||||
#define GPP_E2 183
|
||||
#define GPP_E3 184
|
||||
#define GPP_E4 185
|
||||
#define GPP_E5 186
|
||||
#define GPP_E6 187
|
||||
#define GPP_E7 188
|
||||
#define GPP_E8 189
|
||||
#define GPP_E9 190
|
||||
#define GPP_E10 191
|
||||
#define GPP_E11 192
|
||||
#define GPP_E12 193
|
||||
|
||||
/* Group F */
|
||||
#define GPP_F0 194
|
||||
#define GPP_F1 195
|
||||
#define GPP_F2 196
|
||||
#define GPP_F3 197
|
||||
#define GPP_F4 198
|
||||
#define GPP_F5 199
|
||||
#define GPP_F6 200
|
||||
#define GPP_F7 201
|
||||
#define GPP_F8 202
|
||||
#define GPP_F9 203
|
||||
#define GPP_F10 204
|
||||
#define GPP_F11 205
|
||||
#define GPP_F12 206
|
||||
#define GPP_F13 207
|
||||
#define GPP_F14 208
|
||||
#define GPP_F15 209
|
||||
#define GPP_F16 210
|
||||
#define GPP_F17 211
|
||||
#define GPP_F18 212
|
||||
#define GPP_F19 213
|
||||
#define GPP_F20 214
|
||||
#define GPP_F21 215
|
||||
#define GPP_F22 216
|
||||
#define GPP_F23 217
|
||||
|
||||
#define GPIO_COM3_START GPP_E0
|
||||
#define GPIO_COM3_END GPP_F23
|
||||
#define NUM_GPIO_COM3_PADS (GPIO_COM3_END - GPIO_COM3_START + 1)
|
||||
|
||||
/* Group H */
|
||||
#define GPP_H0 218
|
||||
#define GPP_H1 219
|
||||
#define GPP_H2 220
|
||||
#define GPP_H3 221
|
||||
#define GPP_H4 222
|
||||
#define GPP_H5 223
|
||||
#define GPP_H6 224
|
||||
#define GPP_H7 225
|
||||
#define GPP_H8 226
|
||||
#define GPP_H9 227
|
||||
#define GPP_H10 228
|
||||
#define GPP_H11 229
|
||||
#define GPP_H12 230
|
||||
#define GPP_H13 231
|
||||
#define GPP_H14 232
|
||||
#define GPP_H15 233
|
||||
#define GPP_H16 234
|
||||
#define GPP_H17 235
|
||||
#define GPP_H18 236
|
||||
#define GPP_H19 237
|
||||
#define GPP_H20 238
|
||||
#define GPP_H21 239
|
||||
#define GPP_H22 240
|
||||
#define GPP_H23 241
|
||||
|
||||
/* Group J */
|
||||
#define GPP_J0 242
|
||||
#define GPP_J1 243
|
||||
#define GPP_J2 244
|
||||
#define GPP_J3 245
|
||||
#define GPP_J4 246
|
||||
#define GPP_J5 247
|
||||
#define GPP_J6 248
|
||||
#define GPP_J7 249
|
||||
#define GPP_J8 250
|
||||
#define GPP_J9 251
|
||||
|
||||
/* Group K */
|
||||
#define GPP_K0 252
|
||||
#define GPP_K1 253
|
||||
#define GPP_K2 254
|
||||
#define GPP_K3 255
|
||||
#define GPP_K4 256
|
||||
#define GPP_K5 257
|
||||
#define GPP_K6 258
|
||||
#define GPP_K7 259
|
||||
#define GPP_K8 260
|
||||
#define GPP_K9 261
|
||||
#define GPP_K10 262
|
||||
#define GPP_K11 263
|
||||
#define GPP_SYS_PWROK 264
|
||||
#define GPP_SYS_RESETB 265
|
||||
#define GPP_MLK_RSTB 266
|
||||
|
||||
#define GPIO_COM4_START GPP_H0
|
||||
#define GPIO_COM4_END GPP_MLK_RSTB
|
||||
#define NUM_GPIO_COM4_PADS (GPIO_COM4_END - GPIO_COM4_START + 1)
|
||||
|
||||
/* Group I */
|
||||
#define GPP_I0 267
|
||||
#define GPP_I1 268
|
||||
#define GPP_I2 269
|
||||
#define GPP_I3 270
|
||||
#define GPP_I4 271
|
||||
#define GPP_I5 272
|
||||
#define GPP_I6 273
|
||||
#define GPP_I7 274
|
||||
#define GPP_I8 275
|
||||
#define GPP_I9 276
|
||||
#define GPP_I10 277
|
||||
#define GPP_I11 278
|
||||
#define GPP_I12 279
|
||||
#define GPP_I13 280
|
||||
#define GPP_I14 281
|
||||
|
||||
/* Group JTAG */
|
||||
#define GPP_JTAG_TDO 282
|
||||
#define GPP_JTAG_X 283
|
||||
#define GPP_JTAG_PRDYB 284
|
||||
#define GPP_JTAG_PREQB 285
|
||||
#define GPP_JTAG_TDI 286
|
||||
#define GPP_JTAG_TMS 287
|
||||
#define GPP_JTAG_TCK 288
|
||||
#define GPP_JTAG_PMODE 289
|
||||
#define GPP_JTAG_CPU_TRSTB 290
|
||||
|
||||
#define GPIO_COM5_START GPP_I0
|
||||
#define GPIO_COM5_END GPP_JTAG_CPU_TRSTB
|
||||
#define NUM_GPIO_COM5_PADS (GPIO_COM5_END - GPIO_COM5_START + 1)
|
||||
|
||||
/* Group GPD */
|
||||
#define GPD0 291
|
||||
#define GPD1 292
|
||||
#define GPD2 293
|
||||
#define GPD3 294
|
||||
#define GPD4 295
|
||||
#define GPD5 296
|
||||
#define GPD6 297
|
||||
#define GPD7 298
|
||||
#define GPD8 299
|
||||
#define GPD9 300
|
||||
#define GPD10 301
|
||||
#define GPD11 302
|
||||
#define GPD12 303
|
||||
|
||||
#define GPIO_COM2_START GPD0
|
||||
#define GPIO_COM2_END GPD12
|
||||
#define NUM_GPIO_COM2_PADS (GPIO_COM2_END - GPIO_COM2_START + 1)
|
||||
|
||||
#define TOTAL_GPIO_COMM (COMM_5 + 1)
|
||||
#define TOTAL_PADS 304
|
||||
|
||||
#endif
|
||||
|
|
@ -14,6 +14,7 @@
|
|||
#define PID_GPIOCOM0 0x6e
|
||||
#define PID_GPIOCOM1 0x6d
|
||||
#define PID_GPIOCOM2 0x6c
|
||||
#define PID_GPIOCOM3 0x6b
|
||||
#define PID_GPIOCOM4 0x6a
|
||||
#define PID_GPIOCOM5 0x69
|
||||
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
#include <device/device.h>
|
||||
#include <fsp/util.h>
|
||||
#include <intelblocks/cpulib.h>
|
||||
#include <soc/gpio_soc_defs.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/msr.h>
|
||||
#include <soc/pci_devs.h>
|
||||
|
|
|
|||
Loading…
Reference in New Issue