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mb/var/gimble: Set PsysPmax to 143 W 

This patch adds the setting of PsysPmax to 143 W according to
gimble board design.

BUG=b:206990759
TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is
passed to FSP by enabling FSP log & Boot into the OS

Change-Id: Id6a203f05ecfcc1020a422850d35fa3fa64e01d0
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Chia-Ling Hou 2021-11-16 15:02:07 +08:00 committed by Patrick Georgi
parent 461ff1d3e6
commit 21d7d75796
1 changed files with 1 additions and 0 deletions
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1
src/mainboard/google/brya/variants/gimble/overridetree.cb
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@ -32,6 +32,7 @@ chip soc/intel/alderlake
register "gpio_pm[COMM_4]" = "0" register "gpio_pm[COMM_4]" = "0"
register "gpio_pm[COMM_5]" = "0" register "gpio_pm[COMM_5]" = "0"
register "SaGv" = "SaGv_Enabled" register "SaGv" = "SaGv_Enabled"
register "PsysPmax" = "143"
register "TcssAuxOri" = "1" register "TcssAuxOri" = "1"
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # set MAX to USB2_C1 for eye diagram register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # set MAX to USB2_C1 for eye diagram