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kunimitsu sklrvp: remove unused IedSize 

The skylake code is using IED_REGION_SIZE instead of
devicetree.cb. Drop the the option from the device trees.

BUG=chrome-os-partner:43636
BRANCH=None
TEST=None

Original-Change-Id: Ib252266060fbc6ed0eeaac19a6b79c173c6c9a13
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290932
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Trybot-Ready: David James <davidjames@chromium.org>

Change-Id: Ib08628e163ac27d4c49eddcbec6cab3252abd4aa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11200
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Aaron Durbin 2015-08-05 17:36:36 -05:00
parent ccb01f7245
commit 21df8d950b
2 changed files with 0 additions and 4 deletions
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1
src/mainboard/intel/kunimitsu/devicetree.cb
View File

@ -39,7 +39,6 @@ chip soc/intel/skylake
register "gpe0_en_4" = "0x00000000" register "gpe0_en_4" = "0x00000000"
# Memory related # Memory related
register "IedSize" = "0x0"
register "ProbelessTrace" = "0" register "ProbelessTrace" = "0"
# Lan # Lan

3
src/mainboard/intel/sklrvp/devicetree.cb
View File

@ -68,9 +68,6 @@ chip soc/intel/skylake
# Enable S0ix # Enable S0ix
register "s0ix_enable" = "0" register "s0ix_enable" = "0"
# Memory related
register "IedSize" = "0x0"
# Probeless Trace function # Probeless Trace function
register "ProbelessTrace" = "0" register "ProbelessTrace" = "0"