soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0

A minimum of 100ms delay is required before sending a configuration
request to the downstream components. Since the kernel already adds
100ms, this change drops the extra 100ms delay in TBT PCIe root ports
_PS0 method in order to improve resume time.

BUG=b:177519081
TEST=Boot to kernel and validated various tests on Voxel.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ic392f9af6cd739507a80a4ca3fd126088b513304
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50086
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/tigerlake/acpi/tcss_pcierp.asl

@@ -196,8 +196,6 @@ Method (_PS0, 0, Serialized)
 	If (PMEX == 1) {
 		PMEX = 0  /* Disable Power Management SCI */
 	}
-
-	Sleep(100)  /* Wait for 100ms before return to OS starts any OS activities. */
 }
 
 Method (_PS3, 0, Serialized)