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soc/intel/jasperlake: Enable early caching of RAMTOP region 

Enable early caching of the TOM region to optimize the boot time by
selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config.

Purpose of this feature is to cache the TOM (with a fixed size of
16MB) for all consecutive boots even before calling into the FSP.
Otherwise, this range remains un-cached until postcar boot stage
updates the MTRR programming. FSP-M and late romstage uses this
uncached TOM range for various purposes (like relocating services
between SPI mapped cached memory to DRAM based uncache memory) hence
having the ability to cache this range beforehand would help to
optimize the boot time (more than 50ms as applicable).

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iadbce3124a88cf5be0aebde4a76ec6fd4b670216
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This commit is contained in:
Sean Rhodes 2023-04-19 08:48:33 +01:00 committed by Lean Sheng Tan
parent 51bb3afe9c
commit 21e61847c4
1 changed files with 2 additions and 1 deletions
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3
src/soc/intel/jasperlake/Kconfig
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@ -73,7 +73,8 @@ config CPU_SPECIFIC_OPTIONS
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU
select SOC_INTEL_COMMON_BASECODE
select SOC_INTEL_COMMON_BASECODE_RAMTOP
config DCACHE_RAM_BASE
default 0xfef00000