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AMD geode/lx: Remove generic_sdram.c include

Browse source 
The file under lib/ will be removed with K8 and
Geode LX is the only other platform using it.

Change-Id: Id49d72358ecfc4aae4980e3ae787952073e5c838
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki 2018-05-24 09:56:08 +03:00
parent bb748c5f92
commit 21fa51475d
20 changed files with 30 additions and 18 deletions
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1
src/mainboard/aaeon/pfm-540i_revb/romstage.c
View file

@ -42,7 +42,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
}
#include "northbridge/amd/lx/pll_reset.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"

1
src/mainboard/amd/db800/romstage.c
View file

@ -37,7 +37,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
}
#include "northbridge/amd/lx/pll_reset.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"

1
src/mainboard/amd/f2950/romstage.c
View file

@ -40,7 +40,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
}
#include "northbridge/amd/lx/pll_reset.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"

1
src/mainboard/amd/norwich/romstage.c
View file

@ -33,7 +33,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
}
#include "northbridge/amd/lx/pll_reset.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"

1
src/mainboard/artecgroup/dbe61/romstage.c
View file

@ -45,7 +45,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
}
#include "northbridge/amd/lx/pll_reset.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"

1
src/mainboard/bachmann/ot200/romstage.c
View file

@ -35,7 +35,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
}
#include "northbridge/amd/lx/pll_reset.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"

1
src/mainboard/digitallogic/msm800sev/romstage.c
View file

@ -35,7 +35,6 @@ int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/lx/pll_reset.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"

1
src/mainboard/iei/pcisa-lx-800-r10/romstage.c
View file

@ -38,7 +38,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
}
#include "northbridge/amd/lx/pll_reset.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"

1
src/mainboard/iei/pm-lx-800-r11/romstage.c
View file

@ -41,7 +41,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
}
#include <northbridge/amd/lx/pll_reset.c>
#include <lib/generic_sdram.c>
#include <cpu/amd/geode_lx/cpureginit.c>
#include <cpu/amd/geode_lx/syspreinit.c>
#include <cpu/amd/geode_lx/msrinit.c>

1
src/mainboard/iei/pm-lx2-800-r10/romstage.c
View file

@ -42,7 +42,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
}
#include <northbridge/amd/lx/pll_reset.c>
#include <lib/generic_sdram.c>
#include <cpu/amd/geode_lx/cpureginit.c>
#include <cpu/amd/geode_lx/syspreinit.c>
#include <cpu/amd/geode_lx/msrinit.c>

1
src/mainboard/lippert/hurricane-lx/romstage.c
View file

@ -69,7 +69,6 @@ static int smc_send_config(unsigned char config_data)
#endif
#include "northbridge/amd/lx/pll_reset.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"

1
src/mainboard/lippert/literunner-lx/romstage.c
View file

@ -108,7 +108,6 @@ static int smc_send_config(unsigned char config_data)
}
#include "northbridge/amd/lx/pll_reset.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"

1
src/mainboard/lippert/roadrunner-lx/romstage.c
View file

@ -44,7 +44,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
}
#include "northbridge/amd/lx/pll_reset.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"

1
src/mainboard/lippert/spacerunner-lx/romstage.c
View file

@ -109,7 +109,6 @@ static int smc_send_config(unsigned char config_data)
}
#include "northbridge/amd/lx/pll_reset.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"

1
src/mainboard/pcengines/alix1c/romstage.c
View file

@ -89,7 +89,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
}
#include "northbridge/amd/lx/pll_reset.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"

1
src/mainboard/pcengines/alix2d/romstage.c
View file

@ -86,7 +86,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
}
#include "northbridge/amd/lx/pll_reset.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"

1
src/mainboard/traverse/geos/romstage.c
View file

@ -34,7 +34,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
}
#include "northbridge/amd/lx/pll_reset.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"

1
src/mainboard/winent/pl6064/romstage.c
View file

@ -39,7 +39,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
}
#include "northbridge/amd/lx/pll_reset.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"

1
src/northbridge/amd/lx/Makefile.inc
View file

@ -5,5 +5,6 @@ ramstage-y += northbridgeinit.c
ramstage-y += grphinit.c
romstage-y += raminit.c
romstage-y += generic_sdram.c
endif

29
src/northbridge/amd/lx/generic_sdram.c Normal file
View file

@ -0,0 +1,29 @@
#include <console/console.h>
#include <northbridge/amd/lx/raminit.h>
/* Setup SDRAM */
void sdram_initialize(int controllers, const struct mem_controller *ctrl)
{
int i;
/* Set the registers we can set once to reasonable values */
for (i = 0; i < controllers; i++) {
printk(BIOS_DEBUG, "Ram1.%02x\n", i);
sdram_set_registers(ctrl + i);
}
/* Now setup those things we can auto detect */
for (i = 0; i < controllers; i++) {
printk(BIOS_DEBUG, "Ram2.%02x\n", i);
sdram_set_spd_registers(ctrl + i);
}
/* Now that everything is setup enable the SDRAM.
* Some chipsets do the work for us while on others
* we need to it by hand.
*/
printk(BIOS_DEBUG, "Ram3\n");
sdram_enable(controllers, ctrl);
printk(BIOS_DEBUG, "Ram4\n");
}