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mb/google/bry/anahera{4es}: Disable TCSS port1 

Disable unused TCSS Port1.

BUG=b:223082190
TEST=Build

Change-Id: I63f4b7d89a1e37a00c58201ecc88bb336d0932c9
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Wisley Chen 2022-03-07 13:13:29 +06:00 committed by Felix Held
parent 3e5518d72b
commit 21fb05606f
2 changed files with 4 additions and 0 deletions
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2
src/mainboard/google/brya/variants/anahera/overridetree.cb
View File

@ -73,6 +73,7 @@ chip soc/intel/alderlake
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Smart Card
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
register "tcss_ports[1]" = "TCSS_PORT_EMPTY"
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
@ -139,6 +140,7 @@ chip soc/intel/alderlake
device generic 0 on end
end
end
device ref tbt_pcie_rp1 off end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"

2
src/mainboard/google/brya/variants/anahera4es/overridetree.cb
View File

@ -65,6 +65,7 @@ chip soc/intel/alderlake
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Smart Card
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
register "tcss_ports[1]" = "TCSS_PORT_EMPTY"
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
@ -131,6 +132,7 @@ chip soc/intel/alderlake
device generic 0 on end
end
end
device ref tbt_pcie_rp1 off end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"