soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode

This will allow verstage to write post codes.

BUG=b:215425753
TEST=Boot guybrush and verify PSP post codes are printed
22-01-31 15:12:03.214 (S3->S0)
22-01-31 15:12:03.214   03 04 0f 0e f0 f1 f2 01 10 a0 a2 <--new

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6ceee8fcb094f462de99c07aef8e96425d9c3270
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61522
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/cezanne/psp_verstage/chipset.c

@@ -40,13 +40,3 @@ void platform_report_mode(int developer_mode_enabled)
 	else
 		svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_PRODUCTION);
 }
-
-
-/* Functions below are stub functions for not-yet-implemented PSP features.
- * These functions should be replaced with proper implementations later.
- */
-
-uint32_t svc_write_postcode(uint32_t postcode)
-{
-	return 0;
-}

src/soc/amd/cezanne/psp_verstage/svc.c

@@ -140,3 +140,10 @@ uint32_t svc_set_platform_boot_mode(enum chrome_platform_boot_mode boot_mode)
 	SVC_CALL1(SVC_SET_PLATFORM_BOOT_MODE, (uint32_t)boot_mode, retval);
 	return retval;
 }
+
+uint32_t svc_write_postcode(uint32_t postcode)
+{
+	uint32_t retval = 0;
+	SVC_CALL1(SVC_WRITE_POSTCODE, postcode, retval);
+	return retval;
+}

src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h

@@ -51,6 +51,7 @@
 #define SVC_SHA                             0x69
 #define SVC_CCP_DMA                         0x6A
 #define SVC_SET_PLATFORM_BOOT_MODE          0x6C
+#define SVC_WRITE_POSTCODE                  0x6D
 
 struct mod_exp_params {
 	char		*pExponent;	// Exponent address