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mb/intel/dcp847ske: Make devicetree prettier 

Align contents and fix some redundant comments.

Change-Id: I45fb02ac90fe3d280379b08c9931f1064c71633f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This commit is contained in:
Angel Pons 2020-01-01 21:37:33 +01:00 committed by Nico Huber
parent 8aced763b3
commit 221b894e7d
1 changed files with 28 additions and 27 deletions
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7
src/mainboard/intel/dcp847ske/devicetree.cb
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@ -28,9 +28,10 @@ chip northbridge/intel/sandybridge
end
end
device domain 0x0 on
device pci 00.0 on end # Host bridge Host bridge
device pci 00.0 on end # Host bridge
device pci 01.0 off end # PCIe Bridge for discrete graphics
device pci 02.0 on end # Internal graphics VGA controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "sata_port_map" = "0x1"
@ -46,7 +47,7 @@ chip northbridge/intel/sandybridge
device pci 16.3 off end # Management Engine KT
device pci 19.0 on end # Intel Gigabit Ethernet
device pci 1a.0 off end # USB2 EHCI #2
device pci 1b.0 on end # High Definition Audio Audio controller
device pci 1b.0 on end # HD Audio controller
device pci 1c.0 on end # PCIe Port #1 (unused)
device pci 1c.1 on end # PCIe Port #2 (full-length mPCIe/mSATA)
device pci 1c.2 on end # PCIe Port #3 (half-length mPCIe)
@ -57,7 +58,7 @@ chip northbridge/intel/sandybridge
device pci 1c.7 off end # PCIe Port #8
device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on # LPC bridge PCI-LPC bridge
device pci 1f.0 on # LPC bridge
chip superio/nuvoton/nct6776
device pnp 4e.0 off end # Floppy
device pnp 4e.1 off end # Parallel port