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mb/lenovo/*/romstage: Remove unused include byteorder.h 

Change-Id: I3e500aafd26b7524a6782883b9a30f55b544102d
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33511
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Peter Lemenkov 2019-06-15 17:34:23 +02:00 committed by Nico Huber
parent ca70593d0f
commit 22230687aa
9 changed files with 0 additions and 9 deletions
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1
src/mainboard/lenovo/s230u/romstage.c
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@ -16,7 +16,6 @@
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
#include <cbfs.h> #include <cbfs.h>
#include <arch/byteorder.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <console/console.h> #include <console/console.h>

1
src/mainboard/lenovo/t420s/romstage.c
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@ -15,7 +15,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <arch/byteorder.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>

1
src/mainboard/lenovo/t430s/variants/t430s/romstage.c
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@ -16,7 +16,6 @@
*/ */
#include <option.h> #include <option.h>
#include <arch/byteorder.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>

1
src/mainboard/lenovo/t430s/variants/t431s/romstage.c
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@ -16,7 +16,6 @@
*/ */
#include <option.h> #include <option.h>
#include <arch/byteorder.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <console/console.h> #include <console/console.h>
#include <cbfs.h> #include <cbfs.h>

1
src/mainboard/lenovo/t520/romstage.c
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@ -16,7 +16,6 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <arch/byteorder.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>

1
src/mainboard/lenovo/t530/romstage.c
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@ -16,7 +16,6 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <arch/byteorder.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>

1
src/mainboard/lenovo/x1_carbon_gen1/romstage.c
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@ -18,7 +18,6 @@
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
#include <arch/byteorder.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>

1
src/mainboard/lenovo/x220/romstage.c
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@ -16,7 +16,6 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <arch/byteorder.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>

1
src/mainboard/lenovo/x230/romstage.c
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@ -16,7 +16,6 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <arch/byteorder.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>