soc/amd/common: Initialize STB Spill-to-DRAM
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I547671d2bcfe011566466665b14e151b8ec05430 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
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@ -16,7 +16,6 @@ struct stb_entry_struct {
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};
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void write_stb_to_console(void);
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void init_spill_buffer(void);
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void add_stb_to_timestamp_buffer(void);
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#endif /* AMD_BLOCK_STB_H */
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@ -1 +1,4 @@
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smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_SMU) += smu.c
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bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_SMU) += smu.c
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romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SMU) += smu.c
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SMU) += smu.c
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@ -1,6 +1,7 @@
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config SOC_AMD_COMMON_BLOCK_STB
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bool
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select SOC_AMD_COMMON_BLOCK_SMN
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select SOC_AMD_COMMON_BLOCK_SMU
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help
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Select in the SOC if it supports the Smart Trace Buffer
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@ -9,11 +10,28 @@ if SOC_AMD_COMMON_BLOCK_STB
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config WRITE_STB_BUFFER_TO_CONSOLE
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bool "Write STB entries to the console log"
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default n
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depends on !ENABLE_STB_SPILL_TO_DRAM
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help
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This option will tell coreboot to print the STB buffer at various
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points through the boot process. Note that this will prevent the
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entries from being stored if the Spill-to-DRAM feature is enabled.
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config ENABLE_STB_SPILL_TO_DRAM
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bool "Enable Smart Trace Buffer Spill-to-DRAM"
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default n
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help
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Spill-to-DRAM is an STB feature that extends the buffer from using
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just the small SRAM buffer to a much larger area reserved in main
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memory.
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config AMD_STB_SIZE_IN_MB
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int "Smart Trace Buffer Spill-to-DRAM buffer size in MB"
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default 3
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range 3 16
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depends on ENABLE_STB_SPILL_TO_DRAM
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help
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Size of the STB Spill-to-DRAM buffer in MB.
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config ADD_POSTCODES_TO_STB
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bool "Add coreboot postcodes to STB"
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default y
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@ -1,9 +1,13 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include "commonlib/bsd/cb_err.h"
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#include <amdblocks/smn.h>
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#include <amdblocks/smu.h>
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#include <amdblocks/stb.h>
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#include <bootstate.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <soc/smu.h>
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#include <soc/stb.h>
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#define STB_ENTRIES_PER_ROW 4
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@ -59,9 +63,37 @@ void write_stb_to_console(void)
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if ((i % STB_ENTRIES_PER_ROW) == STB_ENTRIES_PER_ROW - 1)
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printk(BIOS_DEBUG, "\n");
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printed_data = 1;
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}
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}
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static void init_spill_buffer(void *unused)
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{
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struct smu_payload smu_payload = {0};
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uintptr_t stb;
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uint32_t size = CONFIG_AMD_STB_SIZE_IN_MB * MiB;
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int i;
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if (!CONFIG(ENABLE_STB_SPILL_TO_DRAM))
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return;
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stb = (uintptr_t)cbmem_add(CBMEM_ID_AMD_STB, size);
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if (!stb) {
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printk(BIOS_ERR, "Could not allocate cbmem buffer for STB\n");
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return;
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}
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smu_payload.msg[0] = (uint32_t)stb;
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smu_payload.msg[1] = 0;
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smu_payload.msg[2] = size;
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printk(BIOS_DEBUG, "STB spill buffer: allocated %d MiB at %lx\n",
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CONFIG_AMD_STB_SIZE_IN_MB, stb);
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if (send_smu_message(SMC_MSG_SET_S2D_ADDR, &smu_payload) == CB_ERR)
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printk(BIOS_ERR, "Could not enable STB Spill-to-dram\n");
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for (i = 0; i < SMU_NUM_ARGS; i++)
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printk(BIOS_DEBUG, "smu_payload.msg[%d]: 0x%x\n", i, smu_payload.msg[i]);
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}
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static void final_stb_console(void *unused)
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@ -70,4 +102,5 @@ static void final_stb_console(void *unused)
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write_stb_to_console();
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}
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BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, init_spill_buffer, NULL);
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, final_stb_console, NULL);
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