GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/common: Update the comment on CSE Region layout 

The comment indicates CSE's data partition is placed after BP2. But, it
was place after BP1.So, the patch updates the comment to reflect the
CSE Region layout correctly.

TEST=Build the code for Brya and didn't notice any compilation errors

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ic871e2e395de17157f4f526064a26bfad538707f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Sridhar Siricilla 2022-07-06 14:39:01 +05:30 committed by Felix Held
parent 8e10a4826a
commit 22369a1fc2
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/intel/common/block/cse/cse_lite.c
View File

@ -34,9 +34,9 @@
* CSE Firmware supports 3 boot partitions. For CSE Lite SKU, only 2 boot partitions are
* used and 3rd boot partition is set to BP_STATUS_PARTITION_NOT_PRESENT.
* CSE Lite SKU Image Layout:
* ------------- ------------------- ---------------------
* |CSE REGION | => | RO | RW | DATA | => | BP1 | BP2 | DATA |
* ------------- ------------------- ---------------------
* ------------- ------------------ --------------------
* |CSE REGION | => | RO | DATA | RW | => | BP1 | DATA | BP2 |
* ------------- ------------------ --------------------
*/
#define CSE_MAX_BOOT_PARTITIONS 3